2019年10月28日 | C语言常用ARM三个头文件

关于ARM开发，在keil4中进行时，可以直接调用芯片型号的头文件，如S3C2440芯片，可直接调用#include“S3C2440.h"、如S3C2410芯片，可直接调用#include"S3C2410.h"，也可以新建头文件，把下面的内容复制进响应的头文件文本文件中，保存，再在C语言程序中调用这些头文件。

#include"option.h"

#include

#include

#include"def.h"

#include"2440addr.h"

/////////////////////////////////////////////// 

一、def

////////////////////////////////////////////

#ifndef __DEF_H__

#define __DEF_H__

#define U32 unsigned int

#define U16 unsigned short

#define S32 int

#define S16 short int

#define U8  unsigned char

#defineS8  char

//lzd add

#defineBYTEchar

#defineWORD short

#defineDWORDint

#defineUINTU32

#defineLPSTRU8 *

#define TRUE 1   

#define FALSE 0

#define OK1

#define FAIL0

#define ESC_KEY0x1b//('q') 

#endif /*__DEF_H__*/

/////////////////////////////////////////////////////////// 

二、option.h

/**************************************************************

NAME: option.h

DESC: To measuure the USB download speed, the WDT is used.

       To measure up to large time, The WDT interrupt is used.

HISTORY:

Feb.20.2002:Shin, On Pil: Programming start

Mar.25.2002:purnnamu: S3C2400X profile.c is ported for S3C2440X.

Jan.E.2004:DonGo: Modified for S3C2440a.

**************************************************************/

#ifndef __OPTION_H__

#define __OPTION_H__

#ifdef __cplusplus

extern "C" {

#endif

#include "def.h"

#ifndef ADS10

#define ADS10 TRUE

#endif

#define USE_MAINFALSE  // change USE_MAIN value in option.a together  

#define SEMIHOSTINGFALSE

//USE_MAIN & SEMIHOSTING are valid only if ADS10==TRUE.

#if !ADS10

    #undef USE_MAIN

    #define USE_MAINFALSE

#endif

#if !USE_MAIN

    #undef SEMIHOSTING

    #define SEMIHOSTINGFALSE

#endif

#define MEGA(1000000)

///////////////////// clock select ///////////////////////////////////////////////

#define CPU2440ATRUE// else CPU2440X

#define FIN (12000000)

//#define FIN(16934400)

// Main clock

#if FIN==12000000

#define FCLK 405000000

//#define FCLK 304800000

//#define FCLK 400000000

//#define FCLK 451200000

//#define FCLK 532800000

#if FCLK==271500000

#define HCLK (FCLK/2)

#define PCLK (HCLK/2)

#elif FCLK==304800000

#define HCLK (FCLK/3)

#define PCLK (HCLK/2)

#elif FCLK==405000000

#define HCLK (FCLK/3)

#define PCLK (HCLK/2)

#elif FCLK==451200000

#define HCLK (FCLK/4)

#define PCLK (HCLK/2)

#elif FCLK==532800000

#define HCLK (FCLK/4)

#define PCLK (HCLK/2)

#endif

#else//FIN=16.9344MHz

#define FCLK 296352000

#if FCLK==266716800

#define HCLK (FCLK/2)

#define PCLK (HCLK/2)

#elif FCLK==296352000

#define HCLK (FCLK/3)

#define PCLK (HCLK/2)

#elif FCLK==399651840

#define HCLK (FCLK/3)

#define PCLK (HCLK/2)

#elif FCLK==530611200

#define HCLK (FCLK/4)

#define PCLK (HCLK/2)

#elif FCLK==541900800

#define HCLK (FCLK/4)

#define PCLK (HCLK/2)

#endif

#endif

/////////////////////////////////////////////////////////////////////

// USB clock

#define UCLK 48000000

// BUSWIDTH : 16,32

#define BUSWIDTH    (32)

//64MB

// 0x30000000 ~ 0x30ffffff : Download Area (16MB) Cacheable

// 0x31000000 ~ 0x33feffff : Non-Cacheable Area

// 0x33ff0000 ~ 0x33ff47ff : Heap & RW Area

// 0x33ff4800 ~ 0x33ff7fff : FIQ ~ User Stack Area

// 0x33ff8000 ~ 0x33fffeff : Not Useed Area

// 0x33ffff00 ~ 0x33ffffff : Exception & ISR Vector Table

#define_RAM_STARTADDRESS 0x30000000

#define_ISR_STARTADDRESS 0x33ffff00     

#define_MMUTT_STARTADDRESS0x33ff8000

#define_STACK_BASEADDRESS0x33ff8000

#define_NONCACHE_STARTADDRESS0x31000000

#if !USE_MAIN

#define HEAPEND  0x43ff0000     //obsolete if USE_MAIN is TRUE.

#endif

//USB Device Options

#define USBDMA1

#define USBDMA_DEMAND 0//the downloadFileSize should be (64*n)

#define BULK_PKT_SIZE64

#defineUPDATE_REFRESH(IN_HCLK)( rREFRESH = (rREFRESH & ~(0x7ff)) | 2049-(U32)((float)IN_HCLK*7.8/1000000) )

//CLKSEL0/1 Clock selection value define

#defineCLK_HCLK(3)

#defineCLK_PCLK(4)

#defineCLK_DCLK(5)

#ifdef __cplusplus

}

#endif

#endif /*__OPTION_H__*/

//////////////////////////////////////////////////////

三、2440addr.h

////////////////////////////////////////////////////

//=============================================================================

// File Name : 2440addr.h

// Function  : S3C2440 Define Address Register

// History

//   0.0 : Programming start (February 15,2002) -> SOP

// Revision: 03.11.2003 ver 0.0Attatched for 2440

//=============================================================================

#ifndef __2440ADDR_H__

#define __2440ADDR_H__

#ifdef __cplusplus

extern "C" {

#endif

#include "option.h"

// Memory control 

#define rBWSCON    (*(volatile unsigned *)0x48000000)//Bus width & wait status

#define rBANKCON0  (*(volatile unsigned *)0x48000004)//Boot ROM control

#define rBANKCON1  (*(volatile unsigned *)0x48000008)//BANK1 control

#define rBANKCON2  (*(volatile unsigned *)0x4800000c)//BANK2 cControl

#define rBANKCON3  (*(volatile unsigned *)0x48000010)//BANK3 control

#define rBANKCON4  (*(volatile unsigned *)0x48000014)//BANK4 control

#define rBANKCON5  (*(volatile unsigned *)0x48000018)//BANK5 control

#define rBANKCON6  (*(volatile unsigned *)0x4800001c)//BANK6 control

#define rBANKCON7  (*(volatile unsigned *)0x48000020)//BANK7 control

#define rREFRESH   (*(volatile unsigned *)0x48000024)//DRAM/SDRAM refresh

#define rBANKSIZE  (*(volatile unsigned *)0x48000028)//Flexible Bank Size

#define rMRSRB6    (*(volatile unsigned *)0x4800002c)//Mode register set for SDRAM

#define rMRSRB7    (*(volatile unsigned *)0x48000030)//Mode register set for SDRAM

// USB Host

// INTERRUPT

#define rSRCPND     (*(volatile unsigned *)0x4a000000)//Interrupt request status

#define rINTMOD     (*(volatile unsigned *)0x4a000004)//Interrupt mode control

#define rINTMSK     (*(volatile unsigned *)0x4a000008)//Interrupt mask control

#define rPRIORITY   (*(volatile unsigned *)0x4a00000c)//IRQ priority control

#define rINTPND     (*(volatile unsigned *)0x4a000010)//Interrupt request status

#define rINTOFFSET  (*(volatile unsigned *)0x4a000014)//Interruot request source offset

#define rSUBSRCPND  (*(volatile unsigned *)0x4a000018)//Sub source pending

#define rINTSUBMSK  (*(volatile unsigned *)0x4a00001c)//Interrupt sub mask

// DMA

#define rDISRC0     (*(volatile unsigned *)0x4b000000)//DMA 0 Initial source

#define rDISRCC0    (*(volatile unsigned *)0x4b000004)//DMA 0 Initial source control

#define rDIDST0     (*(volatile unsigned *)0x4b000008)//DMA 0 Initial Destination

#define rDIDSTC0    (*(volatile unsigned *)0x4b00000c)//DMA 0 Initial Destination control

#define rDCON0      (*(volatile unsigned *)0x4b000010)//DMA 0 Control

#define rDSTAT0     (*(volatile unsigned *)0x4b000014)//DMA 0 Status

#define rDCSRC0     (*(volatile unsigned *)0x4b000018)//DMA 0 Current source

#define rDCDST0     (*(volatile unsigned *)0x4b00001c)//DMA 0 Current destination

#define rDMASKTRIG0 (*(volatile unsigned *)0x4b000020)//DMA 0 Mask trigger

#define rDISRC1     (*(volatile unsigned *)0x4b000040)//DMA 1 Initial source

#define rDISRCC1    (*(volatile unsigned *)0x4b000044)//DMA 1 Initial source control

#define rDIDST1     (*(volatile unsigned *)0x4b000048)//DMA 1 Initial Destination

#define rDIDSTC1    (*(volatile unsigned *)0x4b00004c)//DMA 1 Initial Destination control

#define rDCON1      (*(volatile unsigned *)0x4b000050)//DMA 1 Control

#define rDSTAT1     (*(volatile unsigned *)0x4b000054)//DMA 1 Status

#define rDCSRC1     (*(volatile unsigned *)0x4b000058)//DMA 1 Current source

#define rDCDST1     (*(volatile unsigned *)0x4b00005c)//DMA 1 Current destination

#define rDMASKTRIG1 (*(volatile unsigned *)0x4b000060)//DMA 1 Mask trigger

#define rDISRC2     (*(volatile unsigned *)0x4b000080)//DMA 2 Initial source

#define rDISRCC2    (*(volatile unsigned *)0x4b000084)//DMA 2 Initial source control

#define rDIDST2     (*(volatile unsigned *)0x4b000088)//DMA 2 Initial Destination

#define rDIDSTC2    (*(volatile unsigned *)0x4b00008c)//DMA 2 Initial Destination control

#define rDCON2      (*(volatile unsigned *)0x4b000090)//DMA 2 Control

#define rDSTAT2     (*(volatile unsigned *)0x4b000094)//DMA 2 Status

#define rDCSRC2     (*(volatile unsigned *)0x4b000098)//DMA 2 Current source

#define rDCDST2     (*(volatile unsigned *)0x4b00009c)//DMA 2 Current destination

#define rDMASKTRIG2 (*(volatile unsigned *)0x4b0000a0)//DMA 2 Mask trigger

#define rDISRC3     (*(volatile unsigned *)0x4b0000c0)//DMA 3 Initial source

#define rDISRCC3    (*(volatile unsigned *)0x4b0000c4)//DMA 3 Initial source control

#define rDIDST3     (*(volatile unsigned *)0x4b0000c8)//DMA 3 Initial Destination

#define rDIDSTC3    (*(volatile unsigned *)0x4b0000cc)//DMA 3 Initial Destination control

#define rDCON3      (*(volatile unsigned *)0x4b0000d0)//DMA 3 Control

#define rDSTAT3     (*(volatile unsigned *)0x4b0000d4)//DMA 3 Status

#define rDCSRC3     (*(volatile unsigned *)0x4b0000d8)//DMA 3 Current source

#define rDCDST3     (*(volatile unsigned *)0x4b0000dc)//DMA 3 Current destination

#define rDMASKTRIG3 (*(volatile unsigned *)0x4b0000e0)//DMA 3 Mask trigger

// CLOCK & POWER MANAGEMENT

#define rLOCKTIME   (*(volatile unsigned *)0x4c000000)//PLL lock time counter

#define rMPLLCON    (*(volatile unsigned *)0x4c000004)//MPLL Control

#define rUPLLCON    (*(volatile unsigned *)0x4c000008)//UPLL Control

#define rCLKCON     (*(volatile unsigned *)0x4c00000c)//Clock generator control

#define rCLKSLOW    (*(volatile unsigned *)0x4c000010)//Slow clock control