[资料分享] 不使用内部三态

Internal tri-state signals are not recommended for FPGAs because the device architecture does not include internal tri-state logic. If designs do use internal tri-states in a flat design, the tri-state logic is typically converted to OR gates or multiplexing logic

 

原因：器件结构不包括内部三态结构！

 

如果设计了三态，自动转化成或门   或者复用逻辑！