54ACQQ373
•
54ACTQ373 Quiet Series Octal Transparent Latch with TRI-STATE Outputs
September 1998
54ACQ373
•
54ACTQ373
Quiet Series Octal Transparent Latch with TRI-STATE
®
Outputs
General Description
The ’ACQ/’ACTQ373 consists of eight latches with
TRI-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch En-
able (LE) is HIGH. When LE is low, the data satisfying the in-
put timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
The ’ACQ/’ACTQ373 utilizes NSC Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series
™
features
GTO
™
output control and undershoot corrector in addition to
a split ground bus for superior performance.
Features
n
I
CC
and I
OZ
reduced by 50%
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Improved latch up immunity
n
Eight latches in a single package
n
TRI-STATE outputs drive bus lines or buffer memory
address registers
n
Outputs source/sink 24 mA
n
Faster prop delays than the standard ’AC/’ACT373
n
4 kV minimum ESD immunity (’ACQ)
n
Standard Military Drawing (SMD)
— ’ACTQ373: 5962-92188
— ’ACQ373: 5962-92178
Logic Symbols
IEEE/IEC
DS100238-1
DS100238-2
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Description
Latch Enable Input
Output Enable Input
TRI-STATE Latch Outputs
GTO
™
is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
™
is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100238
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Connection Diagrams
Pin Assignment for
DIP and Flatpak
Pin Assignment
for LCC
DS100238-4
DS100238-3
Functional Description
The ’ACQ/’ACTQ373 contains eight D-type latches with
TRI-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the stan-
dard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs
LE
X
H
H
L
OE
H
L
L
L
D
n
X
L
H
X
Outputs
O
n
Z
L
H
O
0
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before HIGH to Low transition of Latch Enable
Logic Diagram
DS100238-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
= V
CC
+ 0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
= V
CC
+ 0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latchup Source
or Sink Current
Junction Temperature (T
J
)
CDIP
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
’ACQ
’ACTQ
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
54ACQ/ACTQ
Minimum Input Edge Rate
∆V/∆t
’ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@
3.0V, 4.5V, 5.5V
Minimum Input Edge Rate
∆V/∆t
’ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−55˚C to +125˚C
125 mV/ns
±
50 mA
±
50 mA
−65˚C to +150˚C
125 mV/ns
Note:
All commercial packaging is not recommended for applications requir-
ing greater than 2000 temperature cycles from −40˚C to +125˚C.
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
®
circuits outside databook specifications.
±
300 mA
175˚C
DC Characteristics for ’ACQ Family Devices
Symbol
Parameter
V
CC
(V)
V
IH
Minimum High Level
Input Voltage
V
IL
Maximum Low Level
Input Voltage
V
OH
Minimum High Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
54ACQ
T
A
=
−55˚C to +125˚C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
(Note 2)
V
IN
= V
IL
or V
IH
I
OH
= −12 mA
V
I
OH
= −24 mA
I
OH
= −24 mA
I
OUT
= 50 µA
V
I
OUT
= −50 µA
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
V
OUT
= 0.1V
or V
CC
− 0.1V
Units
Conditions
3.0
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
V
3.0
4.5
5.5
I
IN
Maximum Input
Leakage Current
5.5
0.50
0.50
0.50
V
µA
(Note 2)
V
IN
= V
IL
or V
IH
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 24 mA
V
I
= V
CC
, GND
(Note 4)
±
1.0
3
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DC Characteristics for ’ACQ Family Devices
Symbol
Parameter
V
CC
(V)
I
OLD
I
OHD
I
CC
I
OZ
Minimum Dynamic
(Note 3)
Output Current
Maximum Quiescent
Supply Current
Maximum TRI-STATE
Leakage Current
V
OLP
V
OLV
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Maximum Dynamic V
OL
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
(Continued)
54ACQ
T
A
=
−55˚C to +125˚C
Guaranteed Limits
50
−50
80.0
Units
Conditions
5.5
5.5
5.5
mA
mA
µA
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
V
IN
= V
CC
or GND (Note 4)
V
I
(OE) = V
IL
, V
IH
5.5
5.0
5.0
±
5.0
1.5
−1.2
µA
V
V
I
= V
CC
, GND
V
O
= V
CC
, GND
(Notes 5, 6)
V
(Notes 5, 6)
Note 4:
I
IN
and I
CC
@
3.0V are guaranteed to be less than or equal to the respective limit
@
5.5V V
CC
.
I
CC
for 54ACQ
@
25˚C is identical to 74ACQ
@
25˚C.
Note 5:
Plastic DIP package.
Note 6:
Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output
@
GND.
Note 7:
Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (’ACQ). Input-under-test switching: 5V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f = 1 MHz.
DC Characteristics for ’ACTQ Family Devices
Symbol
Parameter
V
CC
(V)
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
4.5
5.5
4.5
5.5
4.5
5.5
54ACTQ
T
A
=
−55˚C to +125˚C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
(Note 8)
V
IN
= V
IL
or V
IH
I
OH
= −24 mA
I
OH
= −24 mA
I
OUT
= 50 µA
(Note 8)
V
IN
= V
IL
or V
IH
I
OL
= 24 mA
I
OL
= 24 mA
V
I
= V
CC
, GND
V
I
= V
IL
, V
IH
V
O
= V
CC
, GND
V
V
V
V
OUT
= 0.1V
or V
CC
− 0.1V
V
OUT
= 0.1V
or V
CC
− 0.1V
I
OUT
= −50 µA
Units
Conditions
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
3.70
4.70
0.1
0.1
V
V
4.5
5.5
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum TRI-STATE
Leakage Current
5.5
5.5
0.50
0.50
V
µA
µA
±
1.0
±
5.0
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4
DC Characteristics for ’ACTQ Family Devices
Symbol
Parameter
V
CC
(V)
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
Maximum
I
CC
/Input
Minimum Dynamic
Output Current
(Note 9)
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Note 8:
All outputs loaded; thresholds on input associated with output under test.
Note 9:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 10:
I
CC
for 54ACTQ
@
25˚C is identical to 74ACTQ
@
25˚C.
Note 11:
Plastic DIP package.
(Continued)
54ACTQ
T
A
=
−55˚C to +125˚C
Guaranteed Limits
1.6
50
−50
80.0
1.5
−1.2
Units
Conditions
5.5
5.5
5.5
5.5
5.0
5.0
mA
mA
mA
µA
V
V
I
= V
CC
− 2.1V
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
V
IN
= V
CC
or GND (Note 10)
(Notes 11, 12)
V
(Notes 11, 12)
Note 12:
Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output
@
GND.
AC Electrical Characteristics
V
CC
(V)
(Note 13)
Min
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PHZ
, t
PLZ
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Note 13:
Voltage Range 5.0 is 5.0V
±
0.5V.
Voltage Range 3.3 is 3.3V
±
0.3V.
54ACQ
T
A
= −55˚C
to +125˚C
C
L
= 50 pF
Max
15.0
9.5
16.0
9.5
14.5
10.5
12.0
10.5
ns
ns
ns
ns
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Units
Symbol
Parameter
5
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