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INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

•

The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•

The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•

The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT648

Octal bus transceiver/register;

3-state; inverting

Product speciﬁcation

File under Integrated Circuits, IC06

December 1990

Philips Semiconductors

Product speciﬁcation

Octal bus transceiver/register; 3-state;

inverting

FEATURES

•

Independent register for A and B buses

•

Multiplexed real-time and stored data

•

Output capability: bus driver

•

category: MSI

GENERAL DESCRIPTION

The 74HC/HCT648 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT648 consist of bus transceiver circuits with

3-state inverting outputs, D-type flip-flops, and control

circuitry arranged for multiplexed transmission of data

directly from the internal registers. Data on the “A” or “B”

QUICK REFERENCE DATA

GND = 0 V; T

amb

= 25

°C;

= t

= 6 ns

74HC/HCT648

bus will be clocked into the registers as the appropriate

clock (CP

and CP

) goes to a HIGH logic level. Output

enable (OE) and direction (DIR) inputs are provided to

control the transceiver function. In the transceiver mode,

data present at the high-impedance port may be stored in

either the “A” or “B” register, or in both. The select source

inputs (S

and S

) can multiplex stored and real-time

(transparent mode) data. The direction (DIR) input

determines which bus will receive data when OE is active

(LOW). In the isolation mode (OE = HIGH), “A” data may

be stored in the “B” register and/or “B” data may be stored

in the “A” register.

When an output function is disabled, the input function is

still enabled and may be used to store and transmit data.

Only one of the two buses, A or B, may be driven at a time.

The “648” is functionally identical to the “646”, but has

inverting data paths.

TYPICAL

SYMBOL

PHL/

PLH

max

Notes

1. C

is used to determine the dynamic power dissipation (P

µW):

= C

CC2

+∑ (C

CC2

) where:

= input frequency in MHz

= output frequency in MHz

∑

CC2

) = sum of outputs

= output load capacitance in pF

= supply voltage in V

2. For HC the condition is V

= GND to V

For HCT the condition is V

= GND to V

−

1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

PARAMETER

propagation delay A

, B

to B

, A

maximum clock frequency

input capacitance

power dissipation capacitance per

channel

notes 1 and 2

CONDITIONS

= 15 pF; V

= 5 V

3.5

HCT

3.5

MHz

UNIT

December 1990

Philips Semiconductors

Product speciﬁcation

Octal bus transceiver/register; 3-state;

inverting

PIN DESCRIPTION

PIN NO.

4, 5, 6, 7, 8, 9, 10, 11

20, 19, 18, 17, 16, 15, 14, 13

SYMBOL

DIR

to A

GND

to B

NAME AND FUNCTION

74HC/HCT648

A to B clock input (LOW-to-HIGH, edge-triggered)

select A to B source input

direction control input

A data inputs/outputs

ground (0 V)

B data inputs/outputs

output enable input (active LOW)

select B to A source input

B to A clock input (LOW-to-HIGH, edge-triggered)

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors

Product speciﬁcation

Octal bus transceiver/register; 3-state;

inverting

74HC/HCT648

Fig.4 Functional diagram.

FUNCTION TABLE

INPUTS

(1)

Notes

1. H = HIGH voltage level

L = LOW voltage level

X = don’t care

↑

= LOW-to-HIGH level transition

2. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input

functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock

inputs.

DIR

H or L

↑

H or L

↑

H or L

DATA I/O

(2)

FUNCTION

TO A

input

output

input

TO B

input

output

isolation

store A and B data

real-time B data to A bus

stored B data to A bus

real-time A data to B bus

stored A data to B bus

December 1990

Philips Semiconductors

Product speciﬁcation

Octal bus transceiver/register; 3-state;

inverting

74HC/HCT648

Fig.5 Logic diagram.

December 1990

参数对比

与74HC648N3相近的元器件有：74HCT648D、74HCT648N、74HCT648N3、74HC648N、74HC648D。描述及对比如下：

型号	74HC648N3	74HCT648D	74HCT648N	74HCT648N3	74HC648N	74HC648D
描述	Registered Bus Transceiver, 1-Func, 8-Bit, Inverted Output, CMOS, PDIP24,	Registered Bus Transceiver, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO24,	Registered Bus Transceiver, 1-Func, 8-Bit, Inverted Output, CMOS, PDIP24,	Registered Bus Transceiver, 1-Func, 8-Bit, Inverted Output, CMOS, PDIP24,	Registered Bus Transceiver, 1-Func, 8-Bit, Inverted Output, CMOS, PDIP24,	Registered Bus Transceiver, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO24,
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合
包装说明	DIP, DIP24,.3	SOP, SOP24,.4	DIP, DIP24,.6	DIP, DIP24,.3	DIP, DIP24,.6	SOP, SOP24,.4
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
控制类型	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL	INDEPENDENT CONTROL
计数方向	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL
JESD-30 代码	R-PDIP-T24	R-PDSO-G24	R-PDIP-T24	R-PDIP-T24	R-PDIP-T24	R-PDSO-G24
JESD-609代码	e0	e0	e0	e0	e0	e0
逻辑集成电路类型	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
最大I（ol）	0.006 A	0.006 A	0.006 A	0.006 A	0.006 A	0.006 A
位数	8	8	8	8	8	8
功能数量	1	1	1	1	1	1
端子数量	24	24	24	24	24	24
最高工作温度	125 °C	125 °C	125 °C	85 °C	125 °C	125 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
输出极性	INVERTED	INVERTED	INVERTED	INVERTED	INVERTED	INVERTED
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	DIP	SOP	DIP	DIP	DIP	SOP
封装等效代码	DIP24,.3	SOP24,.4	DIP24,.6	DIP24,.3	DIP24,.6	SOP24,.4
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	IN-LINE	SMALL OUTLINE	IN-LINE	IN-LINE	IN-LINE	SMALL OUTLINE
电源	2/6 V	5 V	5 V	5 V	2/6 V	2/6 V
Prop。Delay @ Nom-Sup	41 ns	41 ns	41 ns	58 ns	41 ns	41 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
表面贴装	NO	YES	NO	NO	NO	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	INDUSTRIAL	AUTOMOTIVE	AUTOMOTIVE
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	THROUGH-HOLE	GULL WING	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	GULL WING
端子节距	2.54 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm	1.27 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
触发器类型	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
厂商名称	Philips Semiconductors (NXP Semiconductors N.V.)	-	Philips Semiconductors (NXP Semiconductors N.V.)	Philips Semiconductors (NXP Semiconductors N.V.)	Philips Semiconductors (NXP Semiconductors N.V.)	Philips Semiconductors (NXP Semiconductors N.V.)