Hitachi Single-Chip Microcomputer
H8/520
H D6 4752 08
H D6 4352 08
User’s Manual (Hardware)
Preface
The H8/520 is a high-performance single-chip microcomputer featuring a high-speed CPU with 16-bit
internal data paths and a full complement of on-chip supporting modules. The H8/520 is an ideal
microcontroller for a wide variety of medium-scale devices, including both office and industrial equip-
ment and consumer products.
Its instruction set is designed for fast execution of programs coded in the high-level C language.
On-chip facilities include large RAM and ROM memories, numerous timers, serial I/O, an A/D
converter, I/O ports, and other functions for compact implementation of high-performance application
systems.
The H8/520 is available in both a ZTAT
™
version* with on-chip PROM, ideal for the early stages of
production or for products with frequently-changing specifications, and a masked-ROM version
suitable for volume production.
This manual gives a hardware description of the H8/520. For details of the instruction set, refer to the
H8/500 Series Programming Manual,
which applies to all chips in the H8/500 family.
Note: * ZTAT (Zero Turn-Around Time) is a registered trademark of Hitachi, Ltd.
Contents
Section 1 Overview
.................................................................................................................
1.1
1.2
1.3
Features ................................................................................................................................
Block Diagram .....................................................................................................................
Pin Arrangements and Functions .........................................................................................
1.3.1 Pin Arrangement ......................................................................................................
1.3.2 Pin Functions............................................................................................................
1
1
4
5
5
8
Section 2 MCU Operating Modes and Address Space
................................................... 23
2.1
2.2
2.3
Overview..............................................................................................................................
Mode Descriptions ...............................................................................................................
Address Space Map..............................................................................................................
2.3.1 Page Segmentation ...................................................................................................
2.3.2 Page 0 Address Allocations......................................................................................
Mode Control Register (MDCR) .........................................................................................
23
24
25
25
27
29
2.4
Section 3 CPU
........................................................................................................................... 31
3.1
Overview..............................................................................................................................
3.1.1 Features ....................................................................................................................
3.1.2 Address Space ..........................................................................................................
3.1.3 Register Configuration .............................................................................................
CPU Register Descriptions ..................................................................................................
3.2.1 General Registers .....................................................................................................
3.2.2 Control Registers......................................................................................................
3.2.3 Initial Register Values ..............................................................................................
Data Formats........................................................................................................................
3.3.1 Data Formats in General Registers...........................................................................
3.3.2 Data Formats in Memory .........................................................................................
Instructions...........................................................................................................................
3.4.1 Basic Instruction Formats.........................................................................................
3.4.2 Addressing Modes....................................................................................................
3.4.3 Effective Address Calculation..................................................................................
Instruction Set ......................................................................................................................
3.5.1 Overview ..................................................................................................................
3.5.2 Data Transfer Instructions ........................................................................................
3.5.3 Arithmetic Instructions.............................................................................................
3.5.4 Logic Operations ......................................................................................................
3.5.5 Shift Operations........................................................................................................
3.5.6 Bit Manipulations.....................................................................................................
3.5.7 Branching Instructions .............................................................................................
3.5.8 System Control Instructions .....................................................................................
3.5.9 Short-Format Instructions ........................................................................................
Operating Modes..................................................................................................................
3.6.1 Minimum Mode........................................................................................................
3.6.2 Maximum Mode.......................................................................................................
Basic Operational Timing ....................................................................................................
3.7.1 Overview ..................................................................................................................
3.7.2 On-Chip Memory Access Cycle ..............................................................................
3.7.3 Pin States during On-Chip Memory Access ............................................................
31
31
32
33
34
34
35
40
41
42
43
44
44
45
47
49
49
51
53
54
55
56
57
59
62
62
62
63
63
63
64
65
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF)..................................
3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF)................
3.7.6 External Access Cycle..............................................................................................
CPU States ...........................................................................................................................
3.8.1 Overview ..................................................................................................................
3.8.2 Program Execution State..........................................................................................
3.8.3 Exception-Handling State ........................................................................................
3.8.4 Reset State ................................................................................................................
3.8.5 Power-Down State....................................................................................................
65
66
66
67
67
69
70
70
70
Section 4 Exception Handling
.............................................................................................. 71
Overview..............................................................................................................................
4.1.1 Types of Exception Handling and Their Priority .....................................................
4.1.2 Hardware Exception-Handling Sequence ................................................................
4.1.3 Exception Sources and Vector Table ........................................................................
4.2 Reset.....................................................................................................................................
4.2.1 Overview ..................................................................................................................
4.2.2 Reset Sequence.........................................................................................................
4.2.3 Stack Pointer Initialization .......................................................................................
4.3 Address Error .......................................................................................................................
4.3.1 Instruction Prefetch from Illegal Address ................................................................
4.3.2 Word Data Access at Odd Address ..........................................................................
4.3.3 Off-Chip Address Access in Single-Chip Mode ......................................................
4.4 Trace.....................................................................................................................................
4.5 Interrupts ..............................................................................................................................
4.6 Invalid Instruction................................................................................................................
4.7 Trap Instructions and Zero Divide .......................................................................................
4.8 Cases in Which Exception Handling is Deferred ................................................................
4.8.1 Instructions that Disable Interrupts ..........................................................................
4.8.2 Disabling of Exceptions Immediately after a Reset .................................................
4.8.3 Disabling of Interrupts after a Data Transfer Cycle .................................................
4.9 Stack Status after Completion of Exception Handling ........................................................
4.9.1 PC Value Pushed on Stack for Trace, Interrupts,
Trap Instructions, and Zero Divide Exceptions........................................................
4.9.2 PC Value Pushed on Stack for Address Error and Invalid
Instruction Exceptions..............................................................................................
4.10 Notes on Use of the Stack....................................................................................................
4.1
71
71
72
72
75
75
75
76
79
79
79
79
80
80
82
83
83
84
84
85
86
88
88
88
Section 5 Interrupt Controller
.............................................................................................. 89
5.1
Overview..............................................................................................................................
5.1.1 Features ....................................................................................................................
5.1.2 Block Diagram .........................................................................................................
5.1.3 Register Configuration .............................................................................................
Interrupt Types .....................................................................................................................
5.2.1 External Interrupts....................................................................................................
5.2.2 Internal Interrupts.....................................................................................................
5.2.3 Interrupt Vector Table...............................................................................................
Register Descriptions ...........................................................................................................
5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD)................................................
5.3.2 NMI Control Register (NMICR)—H'FFFC.............................................................
5.3.3 IRQ Control Register (IRQCR)—H'FFFD ..............................................................
Interrupt-Handling Sequence ...............................................................................................
89
89
90
91
91
91
93
94
96
96
97
97
100
5.2
5.3
5.4
5.5
5.6
5.4.1 Interrupt-Handling Flow ..........................................................................................
5.4.2 Stack Status after Interrupt Exception-Handling Sequence .....................................
5.4.3 Timing of Interrupt Exception-Handling Sequence .................................................
Interrupts During Operation of the Data Transfer Controller ..............................................
Interrupt Response Time......................................................................................................
100
103
104
104
107
Section 6 Data Transfer Controller
...................................................................................... 109
6.1
Overview..............................................................................................................................
6.1.1 Features ....................................................................................................................
6.1.2 Block Diagram .........................................................................................................
6.1.3 Register Configuration .............................................................................................
Register Descriptions ...........................................................................................................
6.2.1 Data Transfer Mode Register (DTMR) ....................................................................
6.2.2 Data Transfer Source Address Register (DTSR) .....................................................
6.2.3 Data Transfer Destination Register (DTDR)...........................................................
6.2.4 Data Transfer Count Register (DTCR) ....................................................................
6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED) ......................................
Data Transfer Operation.......................................................................................................
6.3.1 Data Transfer Cycle..................................................................................................
6.3.2 DTC Vector Table.....................................................................................................
6.3.3 Location of Register Information in Memory ..........................................................
6.3.4 Length of Data Transfer Cycle.................................................................................
Procedure for Using the DTC ..............................................................................................
Example ...............................................................................................................................
109
109
109
110
111
111
112
112
112
113
114
114
116
118
118
120
121
6.2
6.3
6.4
6.5
Section 7 Wait-State Controller
............................................................................................ 125
7.1
Overview..............................................................................................................................
7.1.1 Features ....................................................................................................................
7.1.2 Block Diagram .........................................................................................................
7.1.3 Register Configuration .............................................................................................
Wait-State Control Register .................................................................................................
Operation in Each Wait Mode..............................................................................................
7.3.1 Programmable Wait Mode........................................................................................
7.3.2 Pin Wait Mode..........................................................................................................
7.3.3 Pin Auto-Wait Mode ................................................................................................
125
125
126
126
127
128
128
129
131
7.2
7.3
Section 8 Clock Pulse Generator
......................................................................................... 133
8.1
8.2
8.3
Overview..............................................................................................................................
8.1.1 Block Diagram .........................................................................................................
Oscillator Circuit..................................................................................................................
System Clock Divider ..........................................................................................................
133
133
133
136
Section 9 I/O Ports
................................................................................................................... 137
9.1
9.2
Overview..............................................................................................................................
Port 1....................................................................................................................................
9.2.1 Overview ..................................................................................................................
9.2.2 Port 1 Registers ........................................................................................................
9.2.3 Pin Functions in Each Mode ....................................................................................
Port 2....................................................................................................................................
9.3.1 Overview ..................................................................................................................
9.3.2 Port 2 Registers ........................................................................................................
9.3.3 Pin Functions in Each Mode ....................................................................................
137
141
141
143
144
152
152
152
154
9.3
