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Hitachi Single-Chip Microcomputer

H8/520

H D6 4752 08

H D6 4352 08

User’s Manual (Hardware)

Preface

The H8/520 is a high-performance single-chip microcomputer featuring a high-speed CPU with 16-bit

internal data paths and a full complement of on-chip supporting modules. The H8/520 is an ideal

microcontroller for a wide variety of medium-scale devices, including both office and industrial equip-

ment and consumer products.

Its instruction set is designed for fast execution of programs coded in the high-level C language.

On-chip facilities include large RAM and ROM memories, numerous timers, serial I/O, an A/D

converter, I/O ports, and other functions for compact implementation of high-performance application

systems.

The H8/520 is available in both a ZTAT

™

version* with on-chip PROM, ideal for the early stages of

production or for products with frequently-changing specifications, and a masked-ROM version

suitable for volume production.

This manual gives a hardware description of the H8/520. For details of the instruction set, refer to the

H8/500 Series Programming Manual,

which applies to all chips in the H8/500 family.

Note: * ZTAT (Zero Turn-Around Time) is a registered trademark of Hitachi, Ltd.

Contents

Section 1 Overview

.................................................................................................................

1.1

1.2

1.3

Features ................................................................................................................................

Block Diagram .....................................................................................................................

Pin Arrangements and Functions .........................................................................................

1.3.1 Pin Arrangement ......................................................................................................

1.3.2 Pin Functions............................................................................................................

Section 2 MCU Operating Modes and Address Space

................................................... 23

2.1

2.2

2.3

Overview..............................................................................................................................

Mode Descriptions ...............................................................................................................

Address Space Map..............................................................................................................

2.3.1 Page Segmentation ...................................................................................................

2.3.2 Page 0 Address Allocations......................................................................................

Mode Control Register (MDCR) .........................................................................................

2.4

Section 3 CPU

........................................................................................................................... 31

3.1

Overview..............................................................................................................................

3.1.1 Features ....................................................................................................................

3.1.2 Address Space ..........................................................................................................

3.1.3 Register Configuration .............................................................................................

CPU Register Descriptions ..................................................................................................

3.2.1 General Registers .....................................................................................................

3.2.2 Control Registers......................................................................................................

3.2.3 Initial Register Values ..............................................................................................

Data Formats........................................................................................................................

3.3.1 Data Formats in General Registers...........................................................................

3.3.2 Data Formats in Memory .........................................................................................

Instructions...........................................................................................................................

3.4.1 Basic Instruction Formats.........................................................................................

3.4.2 Addressing Modes....................................................................................................

3.4.3 Effective Address Calculation..................................................................................

Instruction Set ......................................................................................................................

3.5.1 Overview ..................................................................................................................

3.5.2 Data Transfer Instructions ........................................................................................

3.5.3 Arithmetic Instructions.............................................................................................

3.5.4 Logic Operations ......................................................................................................

3.5.5 Shift Operations........................................................................................................

3.5.6 Bit Manipulations.....................................................................................................

3.5.7 Branching Instructions .............................................................................................

3.5.8 System Control Instructions .....................................................................................

3.5.9 Short-Format Instructions ........................................................................................

Operating Modes..................................................................................................................

3.6.1 Minimum Mode........................................................................................................

3.6.2 Maximum Mode.......................................................................................................

Basic Operational Timing ....................................................................................................

3.7.1 Overview ..................................................................................................................

3.7.2 On-Chip Memory Access Cycle ..............................................................................

3.7.3 Pin States during On-Chip Memory Access ............................................................

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF)..................................

3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF)................

3.7.6 External Access Cycle..............................................................................................

CPU States ...........................................................................................................................

3.8.1 Overview ..................................................................................................................

3.8.2 Program Execution State..........................................................................................

3.8.3 Exception-Handling State ........................................................................................

3.8.4 Reset State ................................................................................................................

3.8.5 Power-Down State....................................................................................................

Section 4 Exception Handling

.............................................................................................. 71

Overview..............................................................................................................................

4.1.1 Types of Exception Handling and Their Priority .....................................................

4.1.2 Hardware Exception-Handling Sequence ................................................................

4.1.3 Exception Sources and Vector Table ........................................................................

4.2 Reset.....................................................................................................................................

4.2.1 Overview ..................................................................................................................

4.2.2 Reset Sequence.........................................................................................................

4.2.3 Stack Pointer Initialization .......................................................................................

4.3 Address Error .......................................................................................................................

4.3.1 Instruction Prefetch from Illegal Address ................................................................

4.3.2 Word Data Access at Odd Address ..........................................................................

4.3.3 Off-Chip Address Access in Single-Chip Mode ......................................................

4.4 Trace.....................................................................................................................................

4.5 Interrupts ..............................................................................................................................

4.6 Invalid Instruction................................................................................................................

4.7 Trap Instructions and Zero Divide .......................................................................................

4.8 Cases in Which Exception Handling is Deferred ................................................................

4.8.1 Instructions that Disable Interrupts ..........................................................................

4.8.2 Disabling of Exceptions Immediately after a Reset .................................................

4.8.3 Disabling of Interrupts after a Data Transfer Cycle .................................................

4.9 Stack Status after Completion of Exception Handling ........................................................

4.9.1 PC Value Pushed on Stack for Trace, Interrupts,

Trap Instructions, and Zero Divide Exceptions........................................................

4.9.2 PC Value Pushed on Stack for Address Error and Invalid

Instruction Exceptions..............................................................................................

4.10 Notes on Use of the Stack....................................................................................................

4.1

Section 5 Interrupt Controller

.............................................................................................. 89

5.1

Overview..............................................................................................................................

5.1.1 Features ....................................................................................................................

5.1.2 Block Diagram .........................................................................................................

5.1.3 Register Configuration .............................................................................................

Interrupt Types .....................................................................................................................

5.2.1 External Interrupts....................................................................................................

5.2.2 Internal Interrupts.....................................................................................................

5.2.3 Interrupt Vector Table...............................................................................................

Register Descriptions ...........................................................................................................

5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD)................................................

5.3.2 NMI Control Register (NMICR)—H'FFFC.............................................................

5.3.3 IRQ Control Register (IRQCR)—H'FFFD ..............................................................

Interrupt-Handling Sequence ...............................................................................................

100

5.2

5.3

5.4

5.5

5.6

5.4.1 Interrupt-Handling Flow ..........................................................................................

5.4.2 Stack Status after Interrupt Exception-Handling Sequence .....................................

5.4.3 Timing of Interrupt Exception-Handling Sequence .................................................

Interrupts During Operation of the Data Transfer Controller ..............................................

Interrupt Response Time......................................................................................................

100

103

104

107

Section 6 Data Transfer Controller

...................................................................................... 109

6.1

Overview..............................................................................................................................

6.1.1 Features ....................................................................................................................

6.1.2 Block Diagram .........................................................................................................

6.1.3 Register Configuration .............................................................................................

Register Descriptions ...........................................................................................................

6.2.1 Data Transfer Mode Register (DTMR) ....................................................................

6.2.2 Data Transfer Source Address Register (DTSR) .....................................................

6.2.3 Data Transfer Destination Register (DTDR)...........................................................

6.2.4 Data Transfer Count Register (DTCR) ....................................................................

6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED) ......................................

Data Transfer Operation.......................................................................................................

6.3.1 Data Transfer Cycle..................................................................................................

6.3.2 DTC Vector Table.....................................................................................................

6.3.3 Location of Register Information in Memory ..........................................................

6.3.4 Length of Data Transfer Cycle.................................................................................

Procedure for Using the DTC ..............................................................................................

Example ...............................................................................................................................

109

110

111

112

113

114

116

118

120

121

6.2

6.3

6.4

6.5

Section 7 Wait-State Controller

............................................................................................ 125

7.1

Overview..............................................................................................................................

7.1.1 Features ....................................................................................................................

7.1.2 Block Diagram .........................................................................................................

7.1.3 Register Configuration .............................................................................................

Wait-State Control Register .................................................................................................

Operation in Each Wait Mode..............................................................................................

7.3.1 Programmable Wait Mode........................................................................................

7.3.2 Pin Wait Mode..........................................................................................................

7.3.3 Pin Auto-Wait Mode ................................................................................................

125

126

127

128

129

131

7.2

7.3

Section 8 Clock Pulse Generator

......................................................................................... 133

8.1

8.2

8.3

Overview..............................................................................................................................

8.1.1 Block Diagram .........................................................................................................

Oscillator Circuit..................................................................................................................

System Clock Divider ..........................................................................................................

133

136

Section 9 I/O Ports

................................................................................................................... 137

9.1

9.2

Overview..............................................................................................................................

Port 1....................................................................................................................................

9.2.1 Overview ..................................................................................................................

9.2.2 Port 1 Registers ........................................................................................................

9.2.3 Pin Functions in Each Mode ....................................................................................

Port 2....................................................................................................................................

9.3.1 Overview ..................................................................................................................

9.3.2 Port 2 Registers ........................................................................................................

9.3.3 Pin Functions in Each Mode ....................................................................................

137

141

143

144

152

154

9.3

型号	HD6435208P	HD6475208C	HD6475208CP	HD6475208F	HD6475208P	HD6435208F	HD6435208CP
描述	Microcontroller, MROM, CMOS, PDIP64, SHRINK, DIP-64	Microcontroller, UVPROM, CMOS, CDIP64, WINDOWED, SHRINK, DIP-64	Microcontroller, OTPROM, CMOS, PQCC68, PLASTIC, LCC-68	Microcontroller, OTPROM, CMOS, PQFP64, QFP-64	Microcontroller, OTPROM, CMOS, PDIP64, SHRINK, DIP-64	Microcontroller, MROM, CMOS, PQFP64, QFP-64	Microcontroller, MROM, CMOS, PQCC68, PLASTIC, LCC-68
零件包装代码	DIP	DIP	LCC	QFP	DIP	QFP	LCC
包装说明	SDIP,	WSDIP,	QCCJ,	QFP,	SDIP,	QFP,	QCCJ,
针数	64	64	68	64	64	64	68
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknow
具有ADC	YES	YES	YES	YES	YES	YES	YES
其他特性	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION
地址总线宽度	20	20	20	20	20	20	20
边界扫描	NO	NO	NO	NO	NO	NO	NO
最大时钟频率	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz
DAC 通道	NO	NO	NO	NO	NO	NO	NO
DMA 通道	NO	NO	NO	NO	NO	NO	NO
外部数据总线宽度	8	8	8	8	8	8	8
格式	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
集成缓存	NO	NO	NO	NO	NO	NO	NO
JESD-30 代码	R-PDIP-T64	R-CDIP-T64	S-PQCC-J68	S-PQFP-G64	R-PDIP-T64	S-PQFP-G64	S-PQCC-J68
长度	57.6 mm	57.3 mm	24.2062 mm	14 mm	57.6 mm	14 mm	24.2062 mm
低功率模式	YES	YES	YES	YES	YES	YES	YES
外部中断装置数量	9	9	9	9	9	9	9
I/O 线路数量	50	50	54	50	50	50	50
串行 I/O 数	2	2	2	2	2	2	2
端子数量	64	64	68	64	64	64	68
计时器数量	2	2	2	2	2	2	2
片上数据RAM宽度	8	8	8	8	8	8	8
片上程序ROM宽度	8	8	8	8	8	8	8
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
PWM 通道	NO	NO	NO	NO	NO	NO	NO
封装主体材料	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SDIP	WSDIP	QCCJ	QFP	SDIP	QFP	QCCJ
封装形状	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE	RECTANGULAR	SQUARE	SQUARE
封装形式	IN-LINE, SHRINK PITCH	IN-LINE, WINDOW, SHRINK PITCH	CHIP CARRIER	FLATPACK	IN-LINE, SHRINK PITCH	FLATPACK	CHIP CARRIER
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
RAM（字数）	512	512	512	512	512	512	512
ROM（单词）	16000	16000	16000	16000	16000	16000	16000
ROM可编程性	MROM	UVPROM	OTPROM	OTPROM	OTPROM	MROM	MROM
座面最大高度	5.08 mm	5.6 mm	4.6 mm	3.05 mm	5.08 mm	3.05 mm	4.6 mm
最大压摆率	50 mA	50 mA	50 mA	50 mA	50 mA	50 mA	50 mA
最大供电电压	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	NO	NO	YES	YES	NO	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子形式	THROUGH-HOLE	THROUGH-HOLE	J BEND	GULL WING	THROUGH-HOLE	GULL WING	J BEND
端子节距	1.778 mm	1.778 mm	1.27 mm	0.8 mm	1.778 mm	0.8 mm	1.27 mm
端子位置	DUAL	DUAL	QUAD	QUAD	DUAL	QUAD	QUAD
宽度	19.05 mm	19.05 mm	24.2062 mm	14 mm	19.05 mm	14 mm	24.2062 mm
uPs/uCs/外围集成电路类型	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER
厂商名称	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）	-	-	Hitachi （Renesas ）	Hitachi （Renesas ）
Base Number Matches	-	1	1	1	1	-	-

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