HD6475208F,HD6475208F pdf中文资料,HD6475208F引脚图,HD6475208F电路-Datasheet-电子工程世界

文档预览

Hitachi Single-Chip Microcomputer

H8/520

H D6 4752 08

H D6 4352 08

User’s Manual (Hardware)

Preface

The H8/520 is a high-performance single-chip microcomputer featuring a high-speed CPU with 16-bit

internal data paths and a full complement of on-chip supporting modules. The H8/520 is an ideal

microcontroller for a wide variety of medium-scale devices, including both office and industrial equip-

ment and consumer products.

Its instruction set is designed for fast execution of programs coded in the high-level C language.

On-chip facilities include large RAM and ROM memories, numerous timers, serial I/O, an A/D

converter, I/O ports, and other functions for compact implementation of high-performance application

systems.

The H8/520 is available in both a ZTAT

™

version* with on-chip PROM, ideal for the early stages of

production or for products with frequently-changing specifications, and a masked-ROM version

suitable for volume production.

This manual gives a hardware description of the H8/520. For details of the instruction set, refer to the

H8/500 Series Programming Manual,

which applies to all chips in the H8/500 family.

Note: * ZTAT (Zero Turn-Around Time) is a registered trademark of Hitachi, Ltd.

Contents

Section 1 Overview

.................................................................................................................

1.1

1.2

1.3

Features ................................................................................................................................

Block Diagram .....................................................................................................................

Pin Arrangements and Functions .........................................................................................

1.3.1 Pin Arrangement ......................................................................................................

1.3.2 Pin Functions............................................................................................................

Section 2 MCU Operating Modes and Address Space

................................................... 23

2.1

2.2

2.3

Overview..............................................................................................................................

Mode Descriptions ...............................................................................................................

Address Space Map..............................................................................................................

2.3.1 Page Segmentation ...................................................................................................

2.3.2 Page 0 Address Allocations......................................................................................

Mode Control Register (MDCR) .........................................................................................

2.4

Section 3 CPU

........................................................................................................................... 31

3.1

Overview..............................................................................................................................

3.1.1 Features ....................................................................................................................

3.1.2 Address Space ..........................................................................................................

3.1.3 Register Configuration .............................................................................................

CPU Register Descriptions ..................................................................................................

3.2.1 General Registers .....................................................................................................

3.2.2 Control Registers......................................................................................................

3.2.3 Initial Register Values ..............................................................................................

Data Formats........................................................................................................................

3.3.1 Data Formats in General Registers...........................................................................

3.3.2 Data Formats in Memory .........................................................................................

Instructions...........................................................................................................................

3.4.1 Basic Instruction Formats.........................................................................................

3.4.2 Addressing Modes....................................................................................................

3.4.3 Effective Address Calculation..................................................................................

Instruction Set ......................................................................................................................

3.5.1 Overview ..................................................................................................................

3.5.2 Data Transfer Instructions ........................................................................................

3.5.3 Arithmetic Instructions.............................................................................................

3.5.4 Logic Operations ......................................................................................................

3.5.5 Shift Operations........................................................................................................

3.5.6 Bit Manipulations.....................................................................................................

3.5.7 Branching Instructions .............................................................................................

3.5.8 System Control Instructions .....................................................................................

3.5.9 Short-Format Instructions ........................................................................................

Operating Modes..................................................................................................................

3.6.1 Minimum Mode........................................................................................................

3.6.2 Maximum Mode.......................................................................................................

Basic Operational Timing ....................................................................................................

3.7.1 Overview ..................................................................................................................

3.7.2 On-Chip Memory Access Cycle ..............................................................................

3.7.3 Pin States during On-Chip Memory Access ............................................................

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.7.4 Register Field Access Cycle (Addresses H'FF80 to H'FFFF)..................................

3.7.5 Pin States during Register Field Access (Addresses H'FF80 to H'FFFF)................

3.7.6 External Access Cycle..............................................................................................

CPU States ...........................................................................................................................

3.8.1 Overview ..................................................................................................................

3.8.2 Program Execution State..........................................................................................

3.8.3 Exception-Handling State ........................................................................................

3.8.4 Reset State ................................................................................................................

3.8.5 Power-Down State....................................................................................................

Section 4 Exception Handling

.............................................................................................. 71

Overview..............................................................................................................................

4.1.1 Types of Exception Handling and Their Priority .....................................................

4.1.2 Hardware Exception-Handling Sequence ................................................................

4.1.3 Exception Sources and Vector Table ........................................................................

4.2 Reset.....................................................................................................................................

4.2.1 Overview ..................................................................................................................

4.2.2 Reset Sequence.........................................................................................................

4.2.3 Stack Pointer Initialization .......................................................................................

4.3 Address Error .......................................................................................................................

4.3.1 Instruction Prefetch from Illegal Address ................................................................

4.3.2 Word Data Access at Odd Address ..........................................................................

4.3.3 Off-Chip Address Access in Single-Chip Mode ......................................................

4.4 Trace.....................................................................................................................................

4.5 Interrupts ..............................................................................................................................

4.6 Invalid Instruction................................................................................................................

4.7 Trap Instructions and Zero Divide .......................................................................................

4.8 Cases in Which Exception Handling is Deferred ................................................................

4.8.1 Instructions that Disable Interrupts ..........................................................................

4.8.2 Disabling of Exceptions Immediately after a Reset .................................................

4.8.3 Disabling of Interrupts after a Data Transfer Cycle .................................................

4.9 Stack Status after Completion of Exception Handling ........................................................

4.9.1 PC Value Pushed on Stack for Trace, Interrupts,

Trap Instructions, and Zero Divide Exceptions........................................................

4.9.2 PC Value Pushed on Stack for Address Error and Invalid

Instruction Exceptions..............................................................................................

4.10 Notes on Use of the Stack....................................................................................................

4.1

Section 5 Interrupt Controller

.............................................................................................. 89

5.1

Overview..............................................................................................................................

5.1.1 Features ....................................................................................................................

5.1.2 Block Diagram .........................................................................................................

5.1.3 Register Configuration .............................................................................................

Interrupt Types .....................................................................................................................

5.2.1 External Interrupts....................................................................................................

5.2.2 Internal Interrupts.....................................................................................................

5.2.3 Interrupt Vector Table...............................................................................................

Register Descriptions ...........................................................................................................

5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD)................................................

5.3.2 NMI Control Register (NMICR)—H'FFFC.............................................................

5.3.3 IRQ Control Register (IRQCR)—H'FFFD ..............................................................

Interrupt-Handling Sequence ...............................................................................................

100

5.2

5.3

5.4

5.5

5.6

5.4.1 Interrupt-Handling Flow ..........................................................................................

5.4.2 Stack Status after Interrupt Exception-Handling Sequence .....................................

5.4.3 Timing of Interrupt Exception-Handling Sequence .................................................

Interrupts During Operation of the Data Transfer Controller ..............................................

Interrupt Response Time......................................................................................................

100

103

104

107

Section 6 Data Transfer Controller

...................................................................................... 109

6.1

Overview..............................................................................................................................

6.1.1 Features ....................................................................................................................

6.1.2 Block Diagram .........................................................................................................

6.1.3 Register Configuration .............................................................................................

Register Descriptions ...........................................................................................................

6.2.1 Data Transfer Mode Register (DTMR) ....................................................................

6.2.2 Data Transfer Source Address Register (DTSR) .....................................................

6.2.3 Data Transfer Destination Register (DTDR)...........................................................

6.2.4 Data Transfer Count Register (DTCR) ....................................................................

6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED) ......................................

Data Transfer Operation.......................................................................................................

6.3.1 Data Transfer Cycle..................................................................................................

6.3.2 DTC Vector Table.....................................................................................................

6.3.3 Location of Register Information in Memory ..........................................................

6.3.4 Length of Data Transfer Cycle.................................................................................

Procedure for Using the DTC ..............................................................................................

Example ...............................................................................................................................

109

110

111

112

113

114

116

118

120

121

6.2

6.3

6.4

6.5

Section 7 Wait-State Controller

............................................................................................ 125

7.1

Overview..............................................................................................................................

7.1.1 Features ....................................................................................................................

7.1.2 Block Diagram .........................................................................................................

7.1.3 Register Configuration .............................................................................................

Wait-State Control Register .................................................................................................

Operation in Each Wait Mode..............................................................................................

7.3.1 Programmable Wait Mode........................................................................................

7.3.2 Pin Wait Mode..........................................................................................................

7.3.3 Pin Auto-Wait Mode ................................................................................................

125

126

127

128

129

131

7.2

7.3

Section 8 Clock Pulse Generator

......................................................................................... 133

8.1

8.2

8.3

Overview..............................................................................................................................

8.1.1 Block Diagram .........................................................................................................

Oscillator Circuit..................................................................................................................

System Clock Divider ..........................................................................................................

133

136

Section 9 I/O Ports

................................................................................................................... 137

9.1

9.2

Overview..............................................................................................................................

Port 1....................................................................................................................................

9.2.1 Overview ..................................................................................................................

9.2.2 Port 1 Registers ........................................................................................................

9.2.3 Pin Functions in Each Mode ....................................................................................

Port 2....................................................................................................................................

9.3.1 Overview ..................................................................................................................

9.3.2 Port 2 Registers ........................................................................................................

9.3.3 Pin Functions in Each Mode ....................................................................................

137

141

143

144

152

154

9.3

型号	HD6475208F	HD6475208C	HD6475208CP	HD6475208P	HD6435208F	HD6435208P	HD6435208CP
描述	Microcontroller, OTPROM, CMOS, PQFP64, QFP-64	Microcontroller, UVPROM, CMOS, CDIP64, WINDOWED, SHRINK, DIP-64	Microcontroller, OTPROM, CMOS, PQCC68, PLASTIC, LCC-68	Microcontroller, OTPROM, CMOS, PDIP64, SHRINK, DIP-64	Microcontroller, MROM, CMOS, PQFP64, QFP-64	Microcontroller, MROM, CMOS, PDIP64, SHRINK, DIP-64	Microcontroller, MROM, CMOS, PQCC68, PLASTIC, LCC-68
零件包装代码	QFP	DIP	LCC	DIP	QFP	DIP	LCC
包装说明	QFP,	WSDIP,	QCCJ,	SDIP,	QFP,	SDIP,	QCCJ,
针数	64	64	68	64	64	64	68
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknow
具有ADC	YES	YES	YES	YES	YES	YES	YES
其他特性	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION	CAPTURE/COMPARE UNIT; 2V DATA RETENTION
地址总线宽度	20	20	20	20	20	20	20
边界扫描	NO	NO	NO	NO	NO	NO	NO
最大时钟频率	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz	10 MHz
DAC 通道	NO	NO	NO	NO	NO	NO	NO
DMA 通道	NO	NO	NO	NO	NO	NO	NO
外部数据总线宽度	8	8	8	8	8	8	8
格式	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
集成缓存	NO	NO	NO	NO	NO	NO	NO
JESD-30 代码	S-PQFP-G64	R-CDIP-T64	S-PQCC-J68	R-PDIP-T64	S-PQFP-G64	R-PDIP-T64	S-PQCC-J68
长度	14 mm	57.3 mm	24.2062 mm	57.6 mm	14 mm	57.6 mm	24.2062 mm
低功率模式	YES	YES	YES	YES	YES	YES	YES
外部中断装置数量	9	9	9	9	9	9	9
I/O 线路数量	50	50	54	50	50	50	50
串行 I/O 数	2	2	2	2	2	2	2
端子数量	64	64	68	64	64	64	68
计时器数量	2	2	2	2	2	2	2
片上数据RAM宽度	8	8	8	8	8	8	8
片上程序ROM宽度	8	8	8	8	8	8	8
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
PWM 通道	NO	NO	NO	NO	NO	NO	NO
封装主体材料	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	QFP	WSDIP	QCCJ	SDIP	QFP	SDIP	QCCJ
封装形状	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE
封装形式	FLATPACK	IN-LINE, WINDOW, SHRINK PITCH	CHIP CARRIER	IN-LINE, SHRINK PITCH	FLATPACK	IN-LINE, SHRINK PITCH	CHIP CARRIER
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
RAM（字数）	512	512	512	512	512	512	512
ROM（单词）	16000	16000	16000	16000	16000	16000	16000
ROM可编程性	OTPROM	UVPROM	OTPROM	OTPROM	MROM	MROM	MROM
座面最大高度	3.05 mm	5.6 mm	4.6 mm	5.08 mm	3.05 mm	5.08 mm	4.6 mm
最大压摆率	50 mA	50 mA	50 mA	50 mA	50 mA	50 mA	50 mA
最大供电电压	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	NO	YES	NO	YES	NO	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子形式	GULL WING	THROUGH-HOLE	J BEND	THROUGH-HOLE	GULL WING	THROUGH-HOLE	J BEND
端子节距	0.8 mm	1.778 mm	1.27 mm	1.778 mm	0.8 mm	1.778 mm	1.27 mm
端子位置	QUAD	DUAL	QUAD	DUAL	QUAD	DUAL	QUAD
宽度	14 mm	19.05 mm	24.2062 mm	19.05 mm	14 mm	19.05 mm	24.2062 mm
uPs/uCs/外围集成电路类型	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER	MICROCONTROLLER
Base Number Matches	1	1	1	1	-	-	-
厂商名称	-	Hitachi （Renesas ）	Hitachi （Renesas ）	-	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）

TM4C123GH6PM的ADC数据用uDMA乒乓模式传输不成功，请帮忙看看哪里配置错误，谢谢！: 我的问题中定时器触发ADC转换，转换完后用uDMA将数据搬至缓存区。用乒乓模式，配置了主/副控制结构...; HQing 微控制器 MCU

msp430G2452的启动问题: 我用2452手工焊接了一个小板，然后发现一个问题，就是上电的时候，单片机启动不起来，然后用表笔或者什...; gameboy22 微控制器 MCU

有人用过PADS9.5的HyperLynx做电路仿真吗？: 请问：有人用过PADS9.5的HyperLynx做电路仿真吗？用着咋样？谢谢！有人用过...; yhye2world 综合技术交流

大家知道哪家厂商能帮北京用户定做工控机吗: 需要加几个硬件功能按钮，因而与用户软件之间有一点点接口。大家帮忙推荐一下，哪家工控机制造商（最好是...; aloonling 嵌入式系统

s3c2440显示问题: 我是新手，学校有一个作业想用TX2440这个开发板做，我看了一下带的视频，但是还是不知道怎么完成我的...; 532741697 ARM技术

两个listctrl之间控制的问题: 我在dialog上放两个listctrl：分别是List1，Llist2；我的目的是点List1的...; akumax 嵌入式系统

UG-2864HSWEG0或ssd1306与stm32源程序+Proteus仿真

我在做这个仿真的时候也遇到了一定问题，现附上proteus仿真模拟图和源代码供大家参考。大家在用这块屏幕取字模的时候一定要注意是行列式还是列行试。注意在打印数组的时候要注意他的页与行的变换。加油仿真原理图如下单片机源程序如下: #include sys.h #include usart.h #include delay.h //unsigned char a = mengxiny...[详细]
实时操作系统μC/OS-II在MCF5272上的移植

摘要：介绍了实时操作系统μC/OS-II的特点和内核结构，并首次实现μC/OS-II在Motorola嵌入式处理器MCF5272上的移值。关键词：μC/OS-II MCF5272 移植 GNU工具链作为一个实时内核，μC/OS从1992年开始为人们熟悉，到现在已经发展为μC/OS-II。ΜC/OS-II最多支持56个任务，其内核为占先式，总是执行就绪态的优先级最高的任务，并支持Semap...[详细]
华东科技计划挂牌转让中电熊猫三条液晶面板产线股权

7月22日，*ST东科发布公告称，为调整战略布局，公司拟在上海联合产权交易所将持有的南京中电熊猫平板显示科技有限公司（以下简称“南京平板显示”）57.646%的股权和持有的成都中电熊猫显示科技有限公司（以下简称“成都显示”）全部或部分股权进行预挂牌转让。本次交易将构成重大资产重组，本次交易的交易对方尚未确定，但鉴于中国电子有限公司（以下简称“中国电子”）是公司实际控制人的全资子公司，南京中电熊...[详细]
Vishay推出业界首款采用紧凑0603封装尺寸的0.4W检流电阻

日前，Vishay Intertechnology, Inc.（NYSE 股市代号：VSH）宣布，推出新款表面贴装Power Metal Strip®电阻 --- WSLP0603，该电阻是业界首款采用紧凑0603封装尺寸的0.4W检流电阻。WSLP0603电阻的阻值范围非常低，只有10mΩ～100mΩ，可在+170℃的高温下工作。 WSLP0603的小尺寸使其...[详细]
利用NI LabVIEW的并行化技术来提高测试的吞吐量

　　概览　　二十世纪一位很有影响力的建筑设计师Frank Floyd Wright曾经说过：“每个伟大的建筑设计师都是他所处时代的伟大解读者。”这句话同样适用于测试系统设计师们。在他们设计、开发和实现系统的时候，他们必须理解不断进步的技术，如多核处理器、现场可编程门阵列(FPGA)和高速数据总线，如PCI Express等等。通过将这些技术与NI LabVIEW并行化编程软件及NI Tes...[详细]
STRATASYS助力四川大学匹兹堡学院培养高层次科技人才

3D打印和增材制造解决方案供应商Stratasys与四川大学匹兹堡学院宣布建立合作关系，并举行了校企合作协议签约暨增材制造创新实验室的揭牌仪式。Stratasys将为四川大学匹兹堡学院提供专门的定制化3D打印课程与认证，为其培养创新型3D打印技术人才提供强力支撑。此举标志着国内高校在增材制造和3D打印专业人才培养方面迈出了坚实一步，将在四川地区和全国探索产教融合培养模式过程中发挥示范引领作用。 ...[详细]
华为：脸上有遮挡物也有被人脸识别可能

华为早在2015年就这样的技术问题进行了研究，并研发了出了一种人脸识别技术，用以解决存在遮挡物的人脸图像识别精确度较低，甚至是无法识别存在遮挡物的人脸图像的问题。人脸识别技术已经被广泛应用到视频监控、考勤记录、门禁等场合，在视频监控等非主动配合的场景下，如图1所示为现有技术中的人脸识别的流程图：图1 现有的人脸识别方法是在进人脸识别之前，首先建立提取得到的各个人脸特征建立人脸...[详细]
国统计局：4月集成电路产量同比下滑12.1%

据国家统计局今日公布的规模以上工业生产月度数据，4月份计算机、通信和其他电子设备制造业规模以上企业产值同比增长4.9%，主要产品产量中，集成电路当月生产259亿块，同比下滑12.1%，1-4月累计产量1074亿块，同比下滑5.4%，其他产品中，微型计算机设备当月生产3035万台，同比下跌16.8%，移动通信手持机产量1.27亿部，同比下滑1.6%。 ...[详细]
锂离子电池技术开发商Enevate获得8100万美元E轮融资

据外媒报道，锂离子电池技术开发商Enevate获得8100万美元的E轮融资，由富达管理研究公司（Fidelity Management & Research Company）领投，其现有投资者Mission Ventures和Infinite Potential Technologies也参加了这一轮融资。截止目前，Enevate共融资1.91亿美元。Enevate主要研发以硅为主导的锂离子(L...[详细]
华为终端CEO万飚调任海外董事长余承东兼任

　　华为终端CEO 万飚新浪科技讯 5月6日消息，已证实的消息称，华为终端终端CEO万飚调任华为公司俄罗斯地区部总裁，负责在俄罗斯地区的业务开展，并不再同时担任华为终端CEO一职，该职位由华为终端董事长余承东接任。　　万飚是2011年元旦接手终端部门担任CEO的，调任华为俄罗斯地区部总裁后，他将统筹负责华为在俄罗斯地区的运营商业务、消费者终端业务、企业业务。俄罗斯地区部是华为海外市...[详细]
STM32F7实现ADC采集（软件触发+DMA传输）解决了采样结果不实时更新的问题

前面我们虽然实现了STM32F7实现ADC采集（软件触发+DMA传输），但数据只有第一次更新。先仔细研究了下一些配置的参数： ADC1DMA_Handler.Init.Mode DMA的正常模式（DMA_NORMAL）：采集到DMA_BufferSize 的个数后，DMA停止。 DMA的循环模式（DMA_CIRCULAR）：采集到DMA_BufferSize 的个数后，重新回到设置的R...[详细]
为适配iPhoneX 星巴克将更新店内无线充电垫

在不久前结束的苹果发布会上，苹果终于给自家iPhone系列产品加入了快充和无线充电功能。以后，iPhone用户也可以像安卓用户一样享受无线充电的方便。而现在，对于苹果用户而言又有了一新的利好消息。　　据外媒消息报道，星巴克已经宣布，旗下咖啡门店的无线充电板正在进行更新，以支持苹果公司新推出的iPhone X和iPhone8系列产品。为适配iPhoneX 星巴克将更新店内无线充电垫　　众...[详细]
新时达机器人迎来乔迁之喜将获得更大的产能和更快的交付能力

近日高品质机器人品牌——新时达机器人迎来乔迁之喜，正式入驻新工厂，开启试运行。新时达于2017年8月开工建设新工厂，历时2年4个月落成。新工厂占地4.8万平方米，建筑面积约2.54万平方米。新启用的新时达机器人工厂年产能10，000台机器人和3，500套机器人柔性工作站，目标是建设成为国际领先的机器人制造机器人智能工厂，这意味着新时达机器人将获得更大的产能和更快的交付能力，为客户提供高品...[详细]
多频技术改进数字电源转换

　　几十年来，电源转换器拓扑结构一直以模拟技术为基础。虽然大多数转换器采用开关技术和脉宽调制(PWM)，但出于功率半导体器件在处理层面上的兼容，以及成本效益的考虑，电路构成主要为模拟。不过，这种情况正在改变。在显着提高数据中心和电信系统效率的过程中，模拟技术及其电路暴露出自身的缺点。　　数字电源管理和控制提供实时智能，便于系统开发人员构建电源系统自动适应运行环境的变化，并优化每种特定应用场合...[详细]
9月重卡电池配套：宁德时代占68%、亿纬锂能占11%

2024年9月纯电动/换电式重卡电池装车情况电车汇依据最新终端销量数据及新车公告数据统计显示，2024年9月，纯电动（含换电式）重卡电池装车量达到了2515MWh（2.5GWh）。 2024年9月纯电动/换电式重卡电池整车配套情况（前五名）重卡电池宁德时代是该领域的佼佼者，以1702MWh的装车量占据市场份额的67.67%。宁德时代与多家车企如一汽...[详细]