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STK3NA50

N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

器件类别:分立半导体    晶体管   

厂商名称:ST(意法半导体)

厂商官网:http://www.st.com/

器件标准:

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
ST(意法半导体)
零件包装代码
SFM
包装说明
SOT-82, 3 PIN
针数
3
制造商包装代码
SOT82
Reach Compliance Code
_compli
雪崩能效等级(Eas)
40 mJ
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
500 V
最大漏极电流 (Abs) (ID)
2.7 A
最大漏极电流 (ID)
2.7 A
最大漏源导通电阻
3 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JESD-30 代码
R-PSIP-T3
JESD-609代码
e3
元件数量
1
端子数量
3
工作模式
ENHANCEMENT MODE
最高工作温度
150 °C
封装主体材料
PLASTIC/EPOXY
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT SPECIFIED
极性/信道类型
N-CHANNEL
最大功率耗散 (Abs)
50 W
最大脉冲漏极电流 (IDM)
10.8 A
认证状态
Not Qualified
表面贴装
NO
端子面层
Matte Tin (Sn)
端子形式
THROUGH-HOLE
端子位置
SINGLE
处于峰值回流温度下的最长时间
NOT SPECIFIED
晶体管应用
SWITCHING
晶体管元件材料
SILICON
文档预览
STK3NA50
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
STK3NA50
s
s
s
s
s
s
s
V
DSS
500 V
R
DS( on)
< 3
I
D
2.7 A
TYPICAL R
DS(on)
= 2.4
±
30V GATE TO SOURCE VOLTAGE RATING
100% AVALANCHE TESTED
REPETITIVE AVALANCHE DATA AT 100
o
C
LOW INTRINSIC CAPACITANCES
GATE GHARGE MINIMIZED
REDUCED THRESHOLD VOLTAGE SPREAD
SOT-82
1
2
3
1
2
3
DESCRIPTION
This series of POWER MOSFETS represents the
most advanced high voltage technology. The op-
timized cell layout coupled with a new proprietary
edge termination concur to give the device low
R
DS(on)
and gate charge, unequalled ruggedness
and superior switching performance.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SWITCH MODE POWER SUPPLIES (SMPS)
s
DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
SOT-194
(option)
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
D S
V
DG R
V
GS
I
D
I
D
I
D M
(•)
P
tot
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 kΩ)
Gate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100 C
Drain Current (pulsed)
Total Dissipation at T
c
= 25
o
C
Derating Factor
Storage Temperature
Max. Operating Junction Temperature
o
Value
500
500
±
30
2.7
1.7
10.8
50
0.4
-65 to 150
150
Unit
V
V
V
A
A
A
W
W/
o
C
o
o
C
C
(•) Pulse width limited by safe operating area
November 1996
1/10
STK3NA50
THERMAL DATA
R
thj-cas e
R
thj- amb
R
thj- amb
T
l
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Thermal Resistance Case-sink
Maximum Lead Temperature For Soldering Purpose
Max
Max
Typ
2.5
80
0.7
275
o
o
C/W
C/W
o
C/W
o
C
AVALANCHE CHARACTERISTICS
Symbol
I
A R
E
AS
E
AR
I
A R
Parameter
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max,
δ
< 1%)
Single Pulse Avalanche Energy
(starting T
j
= 25
o
C, I
D
= I
AR
, V
D D
= 50 V)
Repetitive Avalanche Energy
(pulse width limited by T
j
max,
δ
< 1%)
Avalanche Current, Repetitive or Not-Repetitive
(T
c
= 100
o
C, pulse width limited by T
j
max,
δ
< 1%)
Max Value
2.7
40
2
1.7
Unit
A
mJ
mJ
A
ELECTRICAL CHARACTERISTICS
(T
case
= 25
o
C unless otherwise specified)
OFF
Symbol
V
( BR)DSS
I
DS S
I
G SS
Parameter
Drain-source
Breakdown Voltage
Test Conditions
I
D
= 250
µA
V
G S
= 0
Min.
500
25
250
±
100
Typ.
Max.
Unit
V
µA
µA
nA
Zero Gate Voltage
V
DS
= Max Rating
Drain Current (V
GS
= 0) V
DS
= Max Rating x 0.8
Gate-body Leakage
Current (V
D S
= 0)
V
GS
=
±
30 V
T
c
= 125 C
o
ON (∗)
Symbol
V
G S(th)
R
DS( on)
I
D( on)
Parameter
Gate Threshold Voltage V
DS
= V
GS
Static Drain-source On
Resistance
On State Drain Current
V
GS
= 10V
Test Conditions
I
D
= 250
µA
I
D
= 1.5 A
3.3
Min.
2.25
Typ.
3
2.4
Max.
3.75
3
Unit
V
A
V
DS
> I
D( on)
x R
D S(on) max
V
GS
= 10 V
DYNAMIC
Symbol
g
fs
(∗)
C
iss
C
oss
C
rss
Parameter
Forward
Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Test Conditions
V
DS
> I
D( on)
x R
D S(on) max
V
DS
= 25 V
f = 1 MHz
I
D
= 1.5 A
V
G S
= 0
Min.
1.2
Typ.
2.2
370
62
20
485
81
27
Max.
Unit
S
pF
pF
pF
2/10
STK3NA50
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHING ON
Symbol
t
d(on)
t
r
(di/dt)
on
Parameter
Turn-on Time
Rise Time
Turn-on Current Slope
Test Conditions
V
DD
= 250 V I
D
= 1.5 A
V
GS
= 10 V
R
G
= 18
(see test circuit, figure 3)
V
DD
= 400 V I
D
= 3 A
V
GS
= 10 V
R
G
= 18
(see test circuit, figure 5)
V
DD
= 400 V
I
D
= 3 A
V
GS
= 10 V
Min.
Typ.
14
23
340
Max.
20
30
Unit
ns
ns
A/µs
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
21
6
9
28
nC
nC
nC
SWITCHING OFF
Symbol
t
r(Vof f)
t
f
t
c
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
V
DD
= 400 V I
D
= 3 A
R
G
= 18
V
GS
= 10 V
(see test circuit, figure 5)
Min.
Typ.
13
11
26
Max.
18
16
35
Unit
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
I
S D
I
SDM
(•)
V
S D
(∗)
t
rr
Q
rr
I
RRM
Parameter
Source-drain Current
Source-drain Current
(pulsed)
Forward On Voltage
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I
SD
= 2.7 A
V
GS
= 0
350
4.2
24
I
SD
= 3 A di/dt = 100 A/µs
V
DD
= 100 V
T
j
= 150
o
C
(see test circuit, figure 5)
Test Conditions
Min.
Typ.
Max.
2.7
10.8
1.6
Unit
A
A
V
ns
µC
A
(∗) Pulsed: Pulse duration = 300
µs,
duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
3/10
STK3NA50
Derating Curve
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
4/10
STK3NA50
Capacitance Variations
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Turn-on Current Slope
Turn-off Drain-source Voltage Slope
Cross-over Time
5/10
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