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RISC-V 5th workshop
共33课时 11小时44分8秒秒
简介
RISC-V 5th workshop
章节
- 课时1：5th RISC V Workshop Introduction Rick O’Connor, RISC V; Dom Rizzo, Google (6分33秒)
- 课时2：RISC V @ UC San Diego Michael B Taylor, UC San Diego 1 (19分38秒)
- 课时3：Updates on PULPino Florian Zaruba, ETH Zurich 1 (13分22秒)
- 课时4：SiFive FE300 and low cost HiFive Development Board Jack Kang, SiFive (23分3秒)
- 课时5：Rapid silicon prototyping and production for RISC V SoCs Neil Hand, Codasip 1 (28分22秒)
- 课时6：VM threads an alternative model for virtual machines on RISC V Ron Minnich, Google (31分50秒)
- 课时7：A memory model for RISC V Muralidaran Vijayaraghavan, MIT (21分20秒)
- 课时8：A Memory Consistency Model for RISC V Caroline Trippel, Princeton University (28分34秒)
- 课时9：Keynote Address Trust, Transparency and Simplicity Eric Grosse, Google (34分57秒)
- 课时10：RISC V Foundation Update Rick O’Connor, RISC V Foundation (19分29秒)
- 课时11：RISC V Marketing Committee Update Arun Thomas, BAE Systems (9分51秒)
- 课时12：RISC V Technical Committee Update Yunsup Lee, SiFive (15分17秒)
- 课时13：Rocket Chip Project a nonprofit foundation for hosting open source RISC V implementations (20分24秒)
- 课时14：128 bit addressing in RISC V and security Steve Wallach, Micron (25分54秒)
- 课时15：The Challenges of Securing and Authenticating Embedded Devices and a Suggested Approach (17分22秒)
- 课时16：Sanctum Minimal Hardware Extensions for Strong Software Isolation Ilia Lebedev, MIT (34分59秒)
- 课时17：Joined up debugging and analysis in the RISC V world Gajinder Panesar, UltraSoC (30分4秒)
- 课时18：Poster Demo Previews ~ 2min per presenter (15分8秒)
- 课时19：RISC V Workshop Introduction Rick O’Connor, RISC V; Dom Rizzo, Google (18分11秒)
- 课时20：“V” Vector Extension Proposal Krste Asanovic, UC Berkeley & SiFive (40分54秒)
- 课时21：Towards Thousand Core RISC V Shared Memory Systems Quan Nguyen,MIT (19分52秒)
- 课时22：SCRx a family of state of the art RISC V synthesizable cores Alexander Redkin, Synta (8分4秒)
- 课时23：Enabling hardware software co design with RISC V and LLVM Alex Bradbury, lowRISC (24分34秒)
- 课时24：VM threads an alternative model for virtual machines on RISC V Ron Minnich, Google (24分13秒)
- 课时25：Enabling low power, smartphone like graphical UIs for RISC V SoCs Michael Gielda, Ant (24分24秒)
- 课时26：A Fast Instruction Set Simulator for RISC V Maxim Maslov, Esperanto (30分20秒)
- 课时27：Go on RISC VBenjamin Barenblat, Michael Pratt, Google (11分14秒)
- 课时28：A Java Virtual Machine for RISC V Porting the Jikes RVM Martin Maas, UC Berkeley (11分52秒)
- 课时29：YoPuzzle A mRISC V development platform for next generations Elkim Roa, Universidad (15分23秒)
- 课时30：RISC V Community needs Peripheral Cores Elkim Roa, Universidad Industrial de Santander (17分51秒)
- 课时31：Sub microsecond Adaptive Voltage Scaling in a 28nm RISC V SoC Ben Keller, UC Berkeley (35分12秒)
- 课时32：Reprogrammable Redundancy for Cache Vmin Reduction in a 28nm RISC V Processor Brian Zimmer (22分56秒)
- 课时33：RISC V Workshop Conclusion Rick O’Connor, RISC V Foundation; Dom Rizzo, Google (3分1秒)
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