3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q64C
GD25Q64C
DATASHEET
1
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q64C
Contents
1.
2.
3.
4.
5.
6.
7.
FEATURES .................................................................................................................................................. 4
GENERAL DESCRIPTION .......................................................................................................................... 5
MEMORY ORGANIZATION ......................................................................................................................... 7
DEVICE OPERATION .................................................................................................................................. 8
DATA PROTECTION ................................................................................................................................... 9
STATUS REGISTER .................................................................................................................................. 11
COMMANDS DESCRIPTION .................................................................................................................... 13
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
W
RITE
E
NABLE
(WREN) (06H) ............................................................................................................. 16
W
RITE
D
ISABLE
(WRDI) (04H) .............................................................................................................. 16
W
RITE
E
NABLE FOR
V
OLATILE
S
TATUS
R
EGISTER
(50H) ........................................................................ 17
R
EAD
S
TATUS
R
EGISTER
(RDSR) (05H
OR
35H
OR
15H) ...................................................................... 17
W
RITE
S
TATUS
R
EGISTER
(WRSR) (01H
OR
31H
OR
11H) .................................................................... 18
R
EAD
D
ATA
B
YTES
(READ) (03H) ........................................................................................................ 19
R
EAD
D
ATA
B
YTES AT
H
IGHER
S
PEED
(F
AST
R
EAD
) (0BH) ..................................................................... 19
D
UAL
O
UTPUT
F
AST
R
EAD
(3BH) .......................................................................................................... 20
Q
UAD
O
UTPUT
F
AST
R
EAD
(6BH) ......................................................................................................... 21
7.10. D
UAL
I/O F
AST
R
EAD
(BBH) ................................................................................................................. 22
7.11. Q
UAD
I/O F
AST
R
EAD
(EBH) ................................................................................................................. 24
7.12. Q
UAD
I/O W
ORD
F
AST
R
EAD
(E7H) ...................................................................................................... 25
7.13. S
ET
B
URST WITH
W
RAP
(77H) .............................................................................................................. 27
7.14. P
AGE
P
ROGRAM
(PP) (02H) ................................................................................................................. 28
7.15. Q
UAD
P
AGE
P
ROGRAM
(32H)................................................................................................................ 29
7.16. F
AST
P
AGE
P
ROGRAM
(FPP) (F2H) ...................................................................................................... 30
7.17. S
ECTOR
E
RASE
(SE) (20H) .................................................................................................................. 31
7.18. 32KB B
LOCK
E
RASE
(BE) (52H) ........................................................................................................... 31
7.19. 64KB B
LOCK
E
RASE
(BE) (D8H) .......................................................................................................... 32
7.20. C
HIP
E
RASE
(CE) (60/C7H) .................................................................................................................. 32
7.21. D
EEP
P
OWER
-D
OWN
(DP) (B9H) .......................................................................................................... 33
7.22. R
ELEASE FROM
D
EEP
P
OWER
-D
OWN OR
H
IGH
P
ERFORMANCE
M
ODE AND
R
EAD
D
EVICE
ID (RDI) (ABH) 34
7.23. R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (REMS) (90H) .............................................................................. 35
7.24. D
UAL
I/O R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (92H) ............................................................................. 36
7.25. Q
UAD
I/O R
EAD
M
ANUFACTURE
ID/ D
EVICE
ID (94H)............................................................................. 37
7.26. R
EAD
I
DENTIFICATION
(RDID) (9FH) ..................................................................................................... 38
7.27. H
IGH
P
ERFORMANCE
M
ODE
(HPM) (A3H) ............................................................................................. 39
7.28. R
EAD
U
NIQUE
ID (4BH) ........................................................................................................................ 40
7.29. P
ROGRAM
/E
RASE
S
USPEND
(PES) (75H) .............................................................................................. 41
7.30. P
ROGRAM
/E
RASE
R
ESUME
(PER) (7AH)............................................................................................... 42
7.31. E
RASE
S
ECURITY
R
EGISTERS
(44H) ...................................................................................................... 42
7.32. P
ROGRAM
S
ECURITY
R
EGISTERS
(42H) ................................................................................................. 43
2
3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q64C
7.33. R
EAD
S
ECURITY
R
EGISTERS
(48H)........................................................................................................ 44
7.34. E
NABLE
R
ESET
(66H)
AND
R
ESET
(99H) ............................................................................................... 45
7.35. R
EAD
S
ERIAL
F
LASH
D
ISCOVERABLE
P
ARAMETER
(5AH) ........................................................................ 45
8.
ELECTRICAL CHARACTERISTICS ......................................................................................................... 50
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
9.
POWER-ON TIMING .......................................................................................................................... 50
INITIAL DELIVERY STATE................................................................................................................. 50
ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 50
CAPACITANCE MEASUREMENT CONDITIONS .............................................................................. 51
DC CHARACTERISTICS .................................................................................................................... 52
AC CHARACTERISTICS .................................................................................................................... 55
ORDERING INFORMATION ...................................................................................................................... 62
9.1.
V
ALID
P
ART
N
UMBERS
.......................................................................................................................... 63
PACKAGE INFORMATION .................................................................................................................... 65
10.
10.1. P
ACKAGE
SOP8 208MIL ...................................................................................................................... 65
10.2. P
ACKAGE
DIP8 300MIL ........................................................................................................................ 66
10.3. P
ACKAGE
SOP16 300MIL .................................................................................................................... 67
10.4. P
ACKAGE
USON8 (4*4
MM
, 0.45
MM THICKNESS
).................................................................................... 68
10.5. P
ACKAGE
WSON8 (6*5
MM
) .................................................................................................................. 69
10.6. P
ACKAGE
WSON8 (8*6
MM
) .................................................................................................................. 70
10.7. P
ACKAGE
TFBGA-24BALL (6*4
BALL ARRAY
) ....................................................................................... 71
11.
REVISION HISTORY.............................................................................................................................. 72
3
3.3V Uniform Sector
Dual and Quad Serial Flash
1.
◆
GD25Q64C
FEATURES
64M-bit Serial Flash
-8192K-byte
-256 bytes per programmable page
◆
Fast Program/Erase Speed
-Page Program time: 0.6ms typical
-Sector Erase time: 50ms typical
-Block Erase time: 0.15/0.20s typical
-Chip Erase time: 25s typical
◆
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
◆
Flexible Architecture
-Uniform Sector of 4K-byte
-Uniform Block of 32/64K-byte
◆
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-Quad I/O Data transfer up to 480Mbits/s
-Continuous Read With 8/16/32/64-byte Wrap
◆
◆
Low Power Consumption
-1μA typical deep power down current
-1μA typical standby current
Advanced Security Features
-128-Bit Unique ID for each device
-3*1024-Byte Security Registers With OTP Locks
-Discoverable parameters (SFDP) register
◆
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top/Bottom Block protection
◆
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
◆
Minimum 100,000 Program/Erase Cycles
Allows XIP(execute in place)operation
- Continuous Read With 8/16/32/64-Byte Wrap
◆
◆
Package Information
-SOP8 (208mil)
-DIP8 (300mil)
-WSON8 (6*5mm)
-WSON8 (8*6mm)
-TFBGA-24 (6*4 ball array)
-SOP16 (300mil)
-USON8 (4*4mm)
◆
Data retention
-20-year data retention typical
Note:
1. Hardware RESET# PIN is offered on special order. Please contact GigaDevice for details.
4
3.3V Uniform Sector
Dual and Quad Serial Flash
2.
GENERAL DESCRIPTION
GD25Q64C
The GD25Q64C (64M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
Connection Diagram
CS#
SO
(IO1)
WP#
(IO2)
VSS
1
2
Top View
3
4
6
5
8–LEAD SOP/DIP
8
7
VCC
HOLD#
(IO3)
SCLK
SI
(IO0)
CS#
SO
(IO1)
WP#
(IO2)
1
2
Top View
3
8
VCC
7 HOLD#
(IO3)
6 SCLK
SI
5 (IO0)
VSS 4
8–LEAD WSON/USON
Top View
4
NC
3
NC
2
NC
1
VCC
HOLD#
(IO3)
VCC
NC
1
2
16
15
SCLK
WP#
HOLD# NC
(IO2)
(IO3)
NC
SI
(IO0)
NC
NC
NC
NC
NC
NC
NC
NC
3
4
Top View
5
6
14
13
12
11
VSS
SCLK
NC
SI
(IO0)
SO
(IO1)
NC
NC
NC
NC
NC
CS#
NC
NC
NC
NC
CS#
SO
(IO1)
7
8
16-LEAD SOP
10
9
VSS
WP#
(IO2)
A
B
C
D
E
F
24-BALL TFBGA
Pin Description
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
I/O
I
I/O
I/O
I
I/O
I/O
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
5
