FEDL610Q431-02
Issue Date: Feb.8, 2011
ML610Q431/ML610Q432
8-bit Microcontroller with a Built-in LCD driver
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as real-time clock,
synchronous serial port, UART, I
2
C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D
converter, 12-bit successive approximation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation
(read operation) equivalent to mask ROM and is most suitable for battery-driven applications.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
CPU
8-bit RISC CPU (CPU name: nX-U8/100)
Instruction system: 16-bit instructions
Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
On-Chip debug function
Minimum instruction execution time
30.5
s
(@32.768 kHz system clock)
0.24 4s (@4.096 MHz system clock)
Internal memory
Internal 64KBbyte Flash ROM (32K16 bits) (including unusable 1KByte TEST area)
Internal 2KByte Data RAM (20488 bits), 1KByte Display Allocation RAM (1024 x 8bit)
Internal 192Byte RAM for display
Interrupt controller
2 non-maskable interrupt sources (Internal source: 1, External source: 1)
23 maskable interrupt sources (Internal sources: 19, External sources: 4)
Time base counter
Low-speed time base counter
1
channel
Frequency compensation (Compensation range: Approx.
488ppm
to +488ppm. Compensation accuracy: Approx.
0.48ppm)
High-speed time base counter
1
channel
Watchdog timer
Non-maskable interrupt and reset
Free running
Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
Timers
8 bits
4 channels (16-bit configuration available)
1 kHz timer
10 Hz/1 Hz interrupt function
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FEDL610Q431-02
LAPIS Semiconductor
ML610Q431/ML610Q432
Capture
Time base capture
2 channels (4096 Hz to 32 Hz)
PWM
Resolution 16 bits
1 channel
Real time clock
Year, month, day, day of the week, hour, minute, and second registers
Automatic leap year correction
Regular interrupts (0.5 sec, 1 sec, 1 minute, 1 hour)
Alarm interrupt
2 channels (day of the week, hour, minute; month, day hour, minute)
Synchronous serial port
Master/slave selectable
LSB first/MSB first selectable
8-bit length/16-bit length selectable
UART
TXD/RXD
1 channel
Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
Positive logic/negative logic selectable
Built-in baud rate generator
I
2
C bus interface
Master function only
Fast mode (400 kbps@4MH½), standard mode (100 kbps@1MH½, 50kbps@500kHz)
Melody driver
Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
Tone length: 63 types
Tempo: 15 types
Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
RC oscillation type A/D converter
24-bit counter
Time division
2 channels
Successive approximation type A/D converter
12-bit A/D converter
Input
2 channels
General-purpose ports
Non-maskable interrupt input port
1 channel
Input-only port
6 channels (including secondary functions)
Output-only port
3 channels (including secondary functions)
Input/output port
ML610Q431: 22 channels (including secondary functions)
ML610Q432: 14 channels (including secondary functions)
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FEDL610Q431-02
LAPIS Semiconductor
ML610Q431/ML610Q432
LCD driver
Dot matrix can be supported.
ML610Q431: 1024 dots max. (64 seg
16 com)
ML610Q432: 1536 dots max. (64 seg
24 com)
1/1 to 1/24 duty
1/3 or 1/4 bias (built-in bias generation circuit)
Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz)
Bias voltage multiplying clock selectable (8 types)
Contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps)
LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
Programmable display allocation function (available only when 1/1~1/8 duty is selected)
Reset
Reset through the RESET_N pin
Power-on reset generation when powered on
Reset when oscillation stop of the low-speed clock is detected
(“A”version(ML610Q431A/Q432A) don’t have the oscilation stop function.)
Reset by the watchdog timer (WDT) overflow
Power supply voltage detect function
Judgment voltages:
One of 16 levels
Judgment accuracy:
2%
(Typ.)
Clock
Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock)
Crystal oscillation (32.768 kHz)
High-speed clock:
Built-in RC oscillation (500 kHz)
Built-in PLL oscillation (8.192 MHz
2.5%),
crystal/ceramic oscillation (4.096 MHz), external clock
Selection of high-speed clock mode by software:
Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock
Power management
HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation
clock)
Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
Shipment
Chip
ML610Q431-xxxWA (Blank product: ML610Q431-NNNWA)
ML610Q432-xxxWA (Blank product: ML610Q432-NNNWA)
ML610Q431A-xxxWA (Blank product: ML610Q431A-NNNWA)
ML610Q432A-xxxWA (Blank product: ML610Q432A-NNNWA)
144-pin plastic LQFP
ML610Q431-xxxTCZ03A (Blank product: ML610Q431-NNNTCZ03A)
ML610Q432-xxxTCZ03A (Blank product: ML610Q432-NNNTCZ03A)
ML610Q431A-xxxTCZ03A (Blank product: ML610Q431A-NNNTCZ03A)
ML610Q432A-xxxTCZ03A (Blank product: ML610Q432A-NNNTCZ03A)
xxx: ROM code number
Guaranteed operating range
Operating temperature:
20C
to 70C
Operating voltage: V
DD
= 1.1V to 3.6V, AV
DD
= 2.2V to 3.6V
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FEDL610Q431-02
LAPIS Semiconductor
ML610Q431/ML610Q432
BLOCK DIAGRAM
ML610Q431 Block Diagram
Figure 1 show the block diagram of the ML610Q431.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1½3
PSW
Timing
Controller
GREG
0½15
ALU
Instruction
Decoder
ELR1½3
LR
EA
SP
Instruction
Register
Data-bus
RAM
2048byte
Interrupt
Controller
INT
1
INT
4
Power
INT
1
INT
1
INT
1
UART
INT
1
I
2
C
TBC
INT
1
PWM
1kHzTC
INT
1
INT
5
PWM0*
SDA*
SCL*
RXD0*
TXD0*
BUS
Controller
ECSR1½3
DSR/CSR
PC
Program
Memory
(Flash)
64Kbyte
V
PP
On-Chip
ICE
V
DD
V
SS
RESET_N
TEST
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
V
DDL
V
DDX
OSC
RESET &
TEST
INT
1
SSIO
SCK0*
SIN0*
SOUT0*
WDT
IN0*
CS0*
RS0*
RT0*
RCT0*
RCM*
IN1*
CS1*
RS1*
RT1*
AV
DD
AV
SS
V
REF
AIN0, AIN1
RC-ADC
×2
Capture
×2
INT
4
INT
3
8bit Timer
×4
Melody
MD0*
NMI
P00 to P03
P10 to P11
GPIO
P20 to P22
P30 to P35
P40 to P47
PA0 to PA7
COM0 to COM15
SEG0 to SEG63
V
L1
, V
L2
, V
L3
, V
L4
C1, C2, C3, C4
INT
1
12bit-ADC
RTC
Display Allocation
RAM 1024Byte
Display RAM
192Byte
LCD
Driver
BLD
LCD
BIAS
Figure 1 ML610Q431 Block Diagram
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FEDL610Q431-02
LAPIS Semiconductor
ML610Q431/ML610Q432
ML610Q432 Block Diagram
Figure 2 show the block diagram of the ML610Q432.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1½3
PSW
Timing
Controller
GREG
0½15
ALU
Instruction
Decoder
ELR1½3
LR
EA
SP
Instruction
Register
Data-bus
RAM
2048byte
Interrupt
Controller
INT
1
INT
4
Power
INT
1
INT
1
INT
1
UART
INT
1
I
2
C
TBC
INT
1
PWM
1kHzTC
INT
1
INT
5
PWM0*
SDA*
SCL*
RXD0*
TXD0*
BUS
Controller
ECSR1½3
DSR/CSR
PC
Program
Memory
(Flash)
64Kbyte
V
PP
On-Chip
ICE
V
DD
V
SS
RESET_N
TEST
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
V
DDL
V
DDX
OSC
RESET &
TEST
INT
1
SSIO
SCK0*
SIN0*
SOUT0*
WDT
IN0*
CS0*
RS0*
RT0*
RCT0*
RCM*
IN1*
CS1*
RS1*
RT1*
AV
DD
AV
SS
V
REF
AIN0, AIN1
RC-ADC
×2
Capture
×2
INT
4
INT
3
8bit Timer
×4
Melody
MD0*
NMI
P00 to P03
P10 to P11
GPIO
P20 to P22
P30 to P35
P40 to P47
INT
1
12bit-ADC
RTC
Display Allocation
RAM 1024Byte
Display RAM
192Byte
LCD
Driver
COM0 to COM23
SEG0 to SEG63
V
L1
, V
L2
, V
L3
, V
L4
C1, C2, C3, C4
BLD
LCD
BIAS
Figure 2 ML610Q432 Block Diagram
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嵌入式系统