A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc.  How do we design these complex chips?  Answer: CAD software tools.  Learn how to build thesA modern VLSI chip is a remarkably complex beast:  billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks).  How do people manage to design these complicated chips?  Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs.  This is the first step of the design chain, as we move from logic to layout.    Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level).

Recommended Background

Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms).  An understanding of basic digital design:  Boolean algebra, Kmaps, gates and flip flops, finite state machine design.  Linear algebra and calculus at the level of a junior or senior in engineering.  Exposure to basic VLSI at an undergraduate level is nice -- but it’s not necessary.  We will keep the course self-contained, but students with some VLSI will be able to skip some background material.e tools in this class.

人们如何设计这些复杂的芯片？答：一系列计算机辅助设计（CAD）工具对芯片进行抽象描述，并逐步细化到最终设计。本课程主要介绍在建立特定应用集成电路（ASIC）或系统芯片（SoC）设计时所使用的主要设计工具。

• 课时1：Welcome and Introduction (24分59秒)
• 课时2：Computational Boolean Algebra_ Basics (15分7秒)
• 课时3：Computational Boolean Algebra_ Boolean Difference (15分51秒)
• 课时4：Computational Boolean Algebra_ Quantification Operators (13分7秒)
• 课时5：Computational Boolean Algebra_ Application to Logic Network Repair (16分19秒)
• 课时6：Computational Boolean Algebra_ Recursive Tautology (9分48秒)
• 课时7：Computational Boolean Algebra_ Recursive Tautology—URP Implementation (20分49秒)
• 课时8：BDD Basics, Part 1 (15分17秒)
• 课时9：BDD Basics, Part 2 (16分51秒)
• 课时10：BDD Sharing (17分0秒)
• 课时11：BDD Ordering (28分12秒)
• 课时12：Satisfiability (SAT), Part 1 (13分51秒)
• 课时13：Boolean Constraint Propagation (BCP) for SAT (17分56秒)
• 课时14：Using SAT for Logic (25分45秒)
• 课时15：Level Logic_ Basics (9分29秒)
• 课时16：Level Logic_ The Reduce-Expand-Irredundant Optimization Loop (13分6秒)
• 课时17：Level Logic_ Details for One Step_ Expand (20分33秒)
• 课时18：Multilevel Logic and the Boolean Network Model (13分57秒)
• 课时19：Multilevel Logic_ Algebraic Model for Factoring (14分15秒)
• 课时20：Multilevel Logic_ Algebraic Division (14分13秒)
• 课时21：Multilevel Logic_ Role of Kernels and Co-Kernels in Factoring (14分49秒)
• 课时22：Multilevel Logic_ Finding the Kernels (18分28秒)
• 课时23：Mulitlevel Logic and Divisor Extraction—Single Cube Case (14分24秒)
• 课时24：Mulitlevel Logic and Divisor Extraction—Multiple Cube Case (20分38秒)
• 课时25：Multilevel Logic and Divisor Extraction—Finding Prime Rectangles & Summary (10分46秒)
• 课时26：Multilevel Logic—Implicit Don’t Cares, Part 1 (17分42秒)
• 课时27：Multilevel Logic—Implicit Don’t Cares, Part 2 (11分18秒)
• 课时28：Multilevel Logic—Satisfiability Don’t Cares (10分50秒)
• 课时29：Multilevel Logic—Controllability Don’t Cares (19分59秒)
• 课时30：Multilevel Logic—Observability Don’t Cares (17分22秒)

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