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BUK7V4R2-40HX

MOSFET - 阵列 2 个 N 通道(半桥) 40V 98A(Ta) 85W(Ta) 表面贴装型 LFPAK56D

产品类别:分立半导体    晶体管   

制造商:Nexperia

官网地址:https://www.nexperia.com

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BUK7V4R2-40HX概述
Nexperia 双标准电平 N 通道 MOSFET 采用 LFPAK56D 封装 (半桥配置) ,采用 Trench 9 Trench MOS 技术。此产品设计符合 AEC-Q101 标准。

LFPAK56D 封装启用半桥配置
减少印刷电路板布局复杂性
通过减少 3 相电动机驱动器的组件占用空间,实现印刷电路板收缩
由于优化了封装设计,改进了系统级 Rth (j-amb)
更低的寄生电感,支持更高的效率
与 LFPAK56D 双封装尺寸兼容
Advanced AEC-Q101 级 Trench 9 硅技术
低功率损耗,高功率密度
卓越的耐雪崩性能
重复性耐雪崩等级
BUK7V4R2-40HX规格参数
参数名称
属性值
类别
分立半导体;晶体管
厂商名称
Nexperia
系列
Automotive, AEC-Q101, TrenchMOS™
包装
卷带(TR)剪切带(CT)
技术
MOSFET(金属氧化物)
配置
2 个 N 通道(半桥)
漏源电压(Vdss)
40V
25°C 时电流 - 连续漏极 (Id)
98A(Ta)
不同 Id、Vgs 时导通电阻(最大值)
4.2 毫欧 @ 20A,10V
不同 Id 时 Vgs(th)(最大值)
3.6V @ 1mA
不同 Vgs 时栅极电荷 (Qg)(最大值)
37nC @ 10V
不同 Vds 时输入电容 (Ciss)(最大值)
2590pF @ 25V
功率 - 最大值
85W(Ta)
工作温度
-55°C ~ 175°C(TJ)
安装类型
表面贴装型
封装/外壳
SOT-1205,8-LFPAK56
供应商器件封装
LFPAK56D
基本产品编号
BUK7V4
BUK7V4R2-40HX文档预览
BUK7V4R2-40H
11 February 2021
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in
LFPAK56D (half-bridge configuration)
Product data sheet
1. General description
Dual, standard level N-channel MOSFET in an LFPAK56D package
(half-bridge configuration), using Trench 9 TrenchMOS technology. This
product has been designed and qualified to AEC-Q101.
An internal connection is made between the source (S1) of the high-
side FET to the drain (D2) of the low-side FET, making the device ideal
to use as a half-bridge switch in high-performance automotive PWM
applications.
D1
G1
S1, D2
G2
S2
aaa-028081
2. Features and benefits
LFPAK56D package with half-bridge configuration enables:
Reduced PCB layout complexity
PCB shrinkage through reduced component footprint for 3-phase motor drive
Improved system level R
th(j-amb)
due to optimized package design
Lower parasitic inductance to support higher efficiency
Footprint compatibility with LFPAK56D Dual package
Advanced AEC-Q101 grade Trench 9 silicon technology:
Low power losses, high power density
Superior avalanche performance
Repetitive avalanche rated
LFPAK copper clip packaging provides high robustness and reliability
Gull wing leads support high manufacturability and Automated Optical Inspection (AOI)
3. Applications
12 V automotive systems
Powertrain, chassis, body and infotainment applications
Brushless or brushed DC motor drive
DC-to-DC systems
LED lighting
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Limiting values FET1 and FET2
V
DS
I
D
P
tot
drain-source voltage
drain current
total power dissipation
25 °C ≤ T
j
≤ 175 °C
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 2
T
mb
= 25 °C;
Fig. 1
[1]
-
-
-
-
-
-
40
98
85
V
A
W
Conditions
Min
Typ
Max
Unit
Nexperia
BUK7V4R2-40H
Parameter
drain-source on-state
resistance
gate-drain charge
Conditions
V
GS
= 10 V; I
D
= 20 A; T
j
= 25 °C;
Fig. 11
I
D
= 20 A; V
DS
= 32 V; V
GS
= 10 V;
T
j
= 25 °C;
Fig. 13; Fig. 14
I
S
= 20 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 20 V; T
j
= 25 °C
Min
2.5
Typ
3.5
Max
4.2
Unit
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
Symbol
R
DSon
Static characteristics FET1 and FET2
Dynamic characteristics FET1 and FET2
Q
GD
-
4.7
9.4
nC
Source-drain diode FET1 and FET2
Q
r
[1]
recovered charge
-
9.2
-
nC
98A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB,
thermal design and operating temperature.
5. Pinning information
Table 2. Pinning information
Pin
Symbol
Description
1
2
3
4
5
6
7
8
S2
G2
S1
G1
D1
D1
S1, D2
S1, D1
source2
gate2
source1
gate1
drain1
drain1
source1, drain2
source1, drain2
1
2
3
4
Simplified outline
8
7
6
5
Graphic symbol
D1
G1
S1, D2
G2
S2
aaa-028081
LFPAK56D; Dual
LFPAK (SOT1205)
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
BUK7V4R2-40H
LFPAK56D;
Dual LFPAK
Description
plastic, single ended surface mounted package (LFPAK56D); 8
leads
Version
SOT1205
7. Marking
Table 4. Marking codes
Type number
BUK7V4R2-40H
Marking code
74V240H
BUK7V4R2-40H
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
11 February 2021
2 / 13
Nexperia
BUK7V4R2-40H
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
P
tot
I
D
I
DM
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Parameter
drain-source voltage
gate-source voltage
total power dissipation
drain current
peak drain current
storage temperature
junction temperature
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
[2] [3]
Conditions
25 °C ≤ T
j
≤ 175 °C
DC; T
j
= 25 °C
T
mb
= 25 °C;
Fig. 1
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 2
V
GS
= 10 V; T
mb
= 100 °C;
Fig. 2
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C;
Fig. 3
[1]
Min
-
-20
-
-
-
-
-55
-55
-
-
-
Max
40
20
85
98
69.5
393
175
175
85
393
42.3
Unit
V
V
W
A
A
A
°C
°C
A
A
mJ
Limiting values FET1 and FET2
Source-drain diode FET1 and FET2
Avalanche ruggedness FET1 and FET2
non-repetitive drain-
I
D
= 82.6 A; V
sup
≤ 40 V; R
GS
= 50 Ω;
source avalanche energy V
GS
= 10 V; T
j(init)
= 25 °C; unclamped;
Fig. 4
non-repetitive avalanche V
sup
= 40 V; V
GS
= 10 V; T
j(init)
= 25 °C;
current
R
GS
= 50 Ω
I
AS
[1]
[2]
[3]
[4]
[4]
-
82.6
A
98A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB,
thermal design and operating temperature.
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
Protected by 100% test
120
P
der
(%)
80
03aa16
I
D
(A)
100
aaa-032380
80
60
40
40
20
0
0
50
100
150
T
mb
(°C)
200
0
0
25
50
75
100
125
150 175
T
mb
(°C)
200
Fig. 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig. 2.
V
GS
≥ 10 V
(1) 98A continuous current has been successfully
demonstrated during application tests. Practically
the current will be limited by PCB, thermal design
and operating temperature.
Continuous drain current as a function of
mounting base temperature, FET1 and FET2
BUK7V4R2-40H
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
11 February 2021
3 / 13
Nexperia
BUK7V4R2-40H
aaa-032382
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
10
3
Limit R
DSon
= V
DS
/ I
D
10
2
t
p
= 10 µs
100 µs
10
DC
1
1 ms
10 ms
100 ms
I
D
(A)
10
-1
10
-1
1
10
V
DS
(V)
10
2
T
mb
= 25 °C; I
DM
is a single pulse
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and
FET2
I
AL
(A)
10
2
aaa-032381
(1)
10
(2)
1
(3)
10
-1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
(1) T
j (init)
= 25 °C; (2) T
j (init)
= 150 °C; (3) Repetitive Avalanche
Fig. 4.
Avalanche rating; avalanche current as a function of avalanche time, FET1 and FET2
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Parameter
R
th(j-mb)
Conditions
Min
-
Typ
1.64
Max
1.76
Unit
K/W
thermal resistance from
Fig. 5
junction to mounting
base
BUK7V4R2-40H
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
11 February 2021
4 / 13
Nexperia
BUK7V4R2-40H
aaa-032383
Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
10
Z
th(j-mb)
(K/W)
1 δ = 0.5
0.2
0.1
10
-1
0.05
0.02
single shot
10
-2
10
-6
t
p
10
-4
10
-3
10
-2
10
-1
t
T
t
p
(s)
1
P
δ=
t
p
T
10
-5
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration, FET1 and
FET2
10. Characteristics
Table 7. Characteristics
Symbol
Parameter
Static characteristics FET1 and FET2
V
(BR)DSS
drain-source
breakdown voltage
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -40 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
V
GS(th)
gate-source threshold
voltage
I
D
= 1 mA; V
DS
=V
GS
; T
j
= 25 °C;
Fig. 9;
Fig. 10
I
D
= 1 mA; V
DS
=V
GS
; T
j
= 175 °C;
Fig. 10
I
D
= 1 mA; V
DS
=V
GS
; T
j
= -55 °C;
Fig. 10
I
DSS
drain leakage current
V
DS
= 40 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 16 V; V
GS
= 0 V; T
j
= 125 °C
V
DS
= 40 V; V
GS
= 0 V; T
j
= 175 °C
I
GSS
R
DSon
gate leakage current
drain-source on-state
resistance
V
GS
= 20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 20 A; T
j
= 25 °C;
Fig. 11
V
GS
= 10 V; I
D
= 20 A; T
j
= 105 °C;
Fig. 12
V
GS
= 10 V; I
D
= 20 A; T
j
= 125 °C;
Fig. 12
V
GS
= 10 V; I
D
= 20 A; T
j
= 175 °C;
Fig. 12
R
G
Q
G(tot)
Q
GS
Q
GD
gate resistance
total gate charge
gate-source charge
gate-drain charge
f = 1 MHz; T
j
= 25 °C
I
D
= 20 A; V
DS
= 32 V; V
GS
= 10 V;
T
j
= 25 °C;
Fig. 13; Fig. 14
Dynamic characteristics FET1 and FET2
-
-
-
26
7.8
4.7
37
12
9.4
nC
nC
nC
40
-
36
2.4
1
-
-
-
-
-
-
2.5
3.4
3.7
4.5
0.72
43
40.5
40
3
-
-
0.007
0.3
53
2
2
3.5
5.2
5.8
7.2
1.8
-
-
-
3.6
-
4.3
1
10
500
100
100
4.2
6.4
7.2
8.8
4.5
V
V
V
V
V
V
µA
µA
µA
nA
nA
Ω
Conditions
Min
Typ
Max
Unit
BUK7V4R2-40H
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
11 February 2021
5 / 13
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