PSMN013-40VLD
16 August 2021
Dual N-channel 40 V, 13 mOhm standard level MOSFET in
LFPAK56D (half-bridge configuration)
Product data sheet
1. General description
Dual, standard level N-channel MOSFET in an LFPAK56D package (half-
bridge configuration), using NextpowerS3 technology.
An internal connection is made between the source (S1) of the high-side
FET to the drain (D2) of the low-side FET, making the device ideal to use
as a half-bridge switch in high-performance PWM and space constrained
motor drive applications
G1
S1, D2
G2
S2
D1
aaa-028081
2. Features and benefits
•
LFPAK56D package with half-bridge configuration enables:
•
Reduced PCB layout complexity
•
Module shrinkage through reduced component count
•
Improved system level R
th(j-amb)
due to optimized package design
•
Lower parasitic inductance to support higher efficiency
•
Footprint compatibility with LFPAK56D Dual package
NextpowerS3 technology
Low power losses, high power density
Superior avalanche performance
Repetitive avalanche rated
LFPAK copper clip packaging provides high robustness and reliability
Gull wing leads support high manufacturability and Automated Optical Inspection (AOI)
•
•
•
•
•
•
3. Applications
•
•
•
•
Handheld power tools, portable appliance and space constrained applications
Brushless or brushed DC motor drive
DC-to-DC systems
LED lighting
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Limiting values FET1 and FET2
V
DS
I
D
P
tot
T
j
drain-source voltage
drain current
total power dissipation
junction temperature
25 °C ≤ T
j
≤ 175 °C
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 2
T
mb
= 25 °C;
Fig. 1
[1]
-
-
-
-55
-
-
-
-
40
42
46
175
V
A
W
°C
Conditions
Min
Typ
Max
Unit
Nexperia
PSMN013-40VLD
Parameter
drain-source on-state
resistance
Conditions
V
GS
= 10 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 8
V
GS
= 4.5 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 8
I
D
= 10 A; V
DS
= 32 V; V
GS
= 5 V;
Fig. 10; Fig. 11
Min
-
-
0.6
4.7
Typ
11.35
14.04
2.1
7.3
Max
13.6
16.9
4.2
10.2
Unit
mΩ
mΩ
nC
nC
Dual N-channel 40 V, 13 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
Symbol
R
DSon
Static characteristics FET1 and FET2
Dynamic characteristics FET1 and FET2
Q
GD
Q
G(tot)
[1]
gate-drain charge
total gate charge
43A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB,
thermal design and operating temperature.
5. Pinning information
Table 2. Pinning information
Pin
Symbol
Description
1
2
3
4
5
6
7
8
S2
G2
S1
G1
D1
D1
S1, D2
S1, D2
source2
gate2
source1
gate1
drain1
drain1
source1, drain2
source1, drain2
1
2
3
4
Simplified outline
8
7
6
5
Graphic symbol
D1
G1
S1, D2
G2
S2
LFPAK56D; Dual
LFPAK (SOT1205)
aaa-028081
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
PSMN013-40VLD
LFPAK56D;
Dual LFPAK
Description
plastic, single ended surface mounted package
(LFPAK56D); 8 leads
Version
SOT1205
7. Marking
Table 4. Marking codes
Type number
PSMN013-40VLD
Marking code
13DL40V
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
Parameter
drain-source voltage
Conditions
25 °C ≤ T
j
≤ 175 °C
Min
-
Max
40
Unit
V
Limiting values FET1 and FET2
PSMN013-40VLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
2 / 12
Nexperia
PSMN013-40VLD
Parameter
peak drain-source
voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
peak drain current
storage temperature
junction temperature
peak soldering
temperature
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
T
mb
= 25 °C;
Fig. 1
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 2
V
GS
= 10 V; T
mb
= 100 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C;
Fig. 3
[1]
Conditions
t
p
= 20 ns; f = 500 kHz; E
DS(AL)
= 200 nJ;
pulsed
25 °C ≤ T
j
≤ 175 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
Max
45
40
20
46
42
30
169
175
175
260
Unit
V
V
V
W
A
A
A
°C
°C
°C
Dual N-channel 40 V, 13 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
Symbol
V
DSM
V
DGR
V
GS
P
tot
I
D
I
DM
T
stg
T
j
T
sld(M)
Source-drain diode FET1 and FET2
I
S
I
SM
E
DS(AL)S
-
-
-
42
169
10.6
A
A
mJ
Avalanche ruggedness FET1 and FET2
non-repetitive drain-
I
D
= 39.9 A; V
sup
≤ 40 V; R
GS
= 50 Ω;
source avalanche energy V
GS
= 10 V; T
j(init)
= 25 °C; unclamped;
t
p
= 9 µs
non-repetitive avalanche V
sup
= 40 V; V
GS
= 10 V; T
j(init)
= 25 °C;
current
R
GS
= 50 Ω
[2]
I
AS
[1]
[2]
-
39.9
A
43A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB,
thermal design and operating temperature.
Protected by 100% test
120
P
der
(%)
80
03aa16
I
D
(A)
50
aaa-032340
40
30
20
40
10
0
0
50
100
150
T
mb
(°C)
200
0
0
25
50
75
100
125
150 175
T
mb
(°C)
200
Fig. 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig. 2.
V
GS
≥ 5 V
42A continuous current has been successfully
demonstrated during application tests. Practically
the current will be limited by PCB, thermal design
and operating temperature.
Continuous drain current as a function of
mounting base temperature, FET1 and FET2
PSMN013-40VLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
3 / 12
Nexperia
PSMN013-40VLD
aaa-032342
Dual N-channel 40 V, 13 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
t
p
= 10 µs
10
DC
100 µs
1
1 ms
10 ms
100 ms
1
10
10
2
10
-1
10
-1
V
DS
(V)
T
mb
= 25 °C; I
DM
is a single pulse
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and
FET2
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Parameter
R
th(j-mb)
Conditions
Min
-
Typ
3
Max
3.23
Unit
K/W
thermal resistance from
Fig. 4
junction to mounting
base
Z
th(j-mb)
(K/W)
10
aaa-032343
δ = 0.5
1
0.2
0.1
0.05
10
-1
0.02
single shot
P
δ=
t
p
T
t
p
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
T
t
p
(s)
1
Fig. 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration, FET1 and
FET2
PSMN013-40VLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
4 / 12
Nexperia
PSMN013-40VLD
Dual N-channel 40 V, 13 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
10. Characteristics
Table 7. Characteristics
Symbol
Parameter
Static characteristics FET1 and FET2
V
(BR)DSS
V
GS(th)
ΔV
GS(th)
/ΔT
drain-source
breakdown voltage
gate-source threshold
voltage
gate-source threshold
voltage variation with
temperature
drain leakage current
gate leakage current
drain-source on-state
resistance
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
=V
GS
; T
j
= 25 °C
25 °C ≤ T
j
≤ 150 °C
40
36
1.5
-
-
-
1.85
-4.2
-
-
2.2
-
V
V
V
mV/K
Conditions
Min
Typ
Max
Unit
I
DSS
I
GSS
R
DSon
V
DS
= 40 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 16 V; V
GS
= 0 V; T
j
= 125 °C
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 8
V
GS
= 10 V; I
D
= 10 A; T
j
= 175 °C;
Fig. 9
V
GS
= 4.5 V; I
D
= 10 A; T
j
= 25 °C;
Fig. 8
V
GS
= 4.5 V; I
D
= 10 A; T
j
= 175 °C;
Fig. 9
-
-
-
-
-
-
-
-
0.7
4.7
9
-
1.5
0.8
0.7
0.6
0.01
0.14
2
2
11.35
-
14.04
-
1.7
7.3
13.9
7.3
2.5
1.4
1.1
2.1
2.9
829
280
38
5.6
8.1
9.1
6.5
11.5
0.84
5
10
100
100
13.6
26.4
16.9
32.8
4.2
10.2
19.4
-
3.8
2.1
1.6
4.2
-
1160
420
84
-
-
-
-
-
1
µA
µA
nA
nA
mΩ
mΩ
mΩ
mΩ
Ω
nC
nC
nC
nC
nC
nC
nC
V
pF
pF
pF
ns
ns
ns
ns
nC
V
R
G
Q
G(tot)
gate resistance
total gate charge
f = 1 MHz; T
j
= 25 °C
I
D
= 10 A; V
DS
= 32 V; V
GS
= 5 V;
Fig. 10; Fig. 11
I
D
= 10 A; V
DS
= 32 V; V
GS
= 10 V;
Fig. 10; Fig. 11
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V
Dynamic characteristics FET1 and FET2
Q
GS
Q
GS(th)
Q
GS(th-pl)
Q
GD
V
GS(pl)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
oss
V
SD
gate-source charge
pre-threshold gate-
source charge
post-threshold gate-
source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
output charge
source-drain voltage
I
D
= 10 A; V
DS
= 32 V; V
GS
= 5 V;
Fig. 10; Fig. 11
I
D
= 10 A; V
DS
= 32 V;
Fig. 10; Fig. 11
V
DS
= 25 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C;
Fig. 12
-
539
182
11.4
V
DS
= 30 V; R
L
= 3 Ω; V
GS
= 5 V;
R
G(ext)
= 5 Ω
-
-
-
-
-
Source-drain diode FET1 and FET2
I
S
= 10 A; V
GS
= 0 V; T
j
= 25 °C;
Fig. 13
-
PSMN013-40VLD
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2021. All rights reserved
Product data sheet
16 August 2021
5 / 12
