刚接触verilog 语言,按照要求编写了一个程序,驱动8位8段数码管轮流显示1--8
moduleshumaguan(clk,rst,d_out,w_out);inputclk;inputrst;outputd_out;outputw_out;regsec_out;regd_out;regw_out;regcount;always@(posedgeclkornegedgerst)beginif(!rst)beginsec_out=32\'d0;count=4\'d0;endelsebeginse