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Digital VLSI Design (RTL to GDS)
共73课时 19小时57分0秒秒
简介
Bar-Ilan University 83-612: Digital VLSI Design
In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture slides can be found on the EnICS Labs web site at:
https://enicslabs.com/academic-courses/dvd-english/
In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture slides can be found on the EnICS Labs web site at:
https://enicslabs.com/academic-courses/dvd-english/
章节
- 课时1：1a Introduction (10分2秒)
- 课时2：1b Building a Chip (13分50秒)
- 课时3：1c Design Automation (5分42秒)
- 课时4：1d The Chip Design Flow (18分0秒)
- 课时5：Introduction (16分36秒)
- 课时6：2a_ Verilog (6分9秒)
- 课时7：2b_ Verilog Syntax (29分28秒)
- 课时8：2c_ Simple Verilog Examples (14分40秒)
- 课时9：2d_ Verilog FSM Implementation (21分6秒)
- 课时10：2e- Coding Style for RTL - part 1 (21分6秒)
- 课时11：How to write Synthesizeable RTL (34分51秒)
- 课时12：Verilog HDL (29分45秒)
- 课时13：3a_ Logic Synthesis - Part 1 (13分9秒)
- 课时14：3b_ HDL Compilation (2分44秒)
- 课时15：3c- Library Definition (31分51秒)
- 课时16：3d- LEF (12分3秒)
- 课时17：3e_ Liberty (.lib) (14分20秒)
- 课时18：3f- Contents of Standard Cell Libraries (4分0秒)
- 课时19：Logic Synthesis Part 1 (18分34秒)
- 课时20：4a_ Logic Synthesis - Part 2 (17分34秒)
- 课时21：4b_ BDDs and Boolean Minimization (15分29秒)
- 课时22：4c_ Constraint Definition (2分8秒)
- 课时23：4d_ Technology Mapping (21分28秒)
- 课时24：4e_ Verilog for Synthesis - revisited (16分32秒)
- 课时25：4f- Timing Optimization (8分50秒)
- 课时26：Logic Synthesis Part 2 (24分14秒)
- 课时27：5a_ Timing Analysis (10分59秒)
- 课时28：5b_ Timing Constraints (14分38秒)
- 课时29：5c_ Static Timing Analysis (STA) (18分17秒)
- 课时30：5d_ STA Example (12分49秒)
- 课时31：5e_ Design Constraints (SDC) (9分19秒)
- 课时32：5f_ SDC Continued. (22分58秒)
- 课时33：5g_ Timing Reports (18分51秒)
- 课时34：5h_ Multi-Mode Multi-Corner (MMMC) (15分49秒)
- 课时35：Timing Analysis (41分25秒)
- 课时36：6a_ Moving to the Physical Domain (6分57秒)
- 课时37：6b- Multiple Voltage Domains (7分16秒)
- 课时38：6c_ Floorplanning (22分26秒)
- 课时39：6d_ Hierarchical Design (9分59秒)
- 课时40：6e- Power Planning (19分50秒)
- 课时41：Moving to the Physical Domain (24分43秒)
- 课时42：7a_ Standard Cell Placement (6分59秒)
- 课时43：7b_ Random Placement (14分34秒)
- 课时44：7c_ Analytic Placement (14分50秒)
- 课时45：7d- Analytic Placement Example (14分35秒)
- 课时46：7e_ Placement in Practice (12分27秒)
- 课时47：Placement (29分15秒)
- 课时48：8a_ Clock Tree Synthesis (CTS) (19分18秒)
- 课时49：8b_ Clock Distribution (16分59秒)
- 课时50：8c_ Clock Concurrent Optimization (CCOpt) (9分40秒)
- 课时51：8d- Clock Tree Synthesis in EDA Tools (10分55秒)
- 课时52：8e_ Clock Routing and Clock Tree Analysis (12分23秒)
- 课时53：8f_ Clock Generation (4分47秒)
- 课时54：8g_ Clock Domain Crossing (CDC) (8分26秒)
- 课时55：CTS (39分22秒)
- 课时56：9a- Routing (3分9秒)
- 课时57：9b_ Maze Routing (11分37秒)
- 课时58：9c_ Maze Routing (continued) (12分59秒)
- 课时59：9d- Routing in Practice (10分37秒)
- 课时60：9e- Signal Integrity (SI) and Design for Manufacturing (DFM) (19分12秒)
- 课时61：Routing (29分52秒)
- 课时62：10a- Packaging (17分17秒)
- 课时63：10b- I_O Circuits - Digital IOs (15分44秒)
- 课时64：10c- I_O Circuits - Analog IOs, ESD Protection, Pad Configurations (14分35秒)
- 课时65：10d- System-in-Package (SiP) (7分23秒)
- 课时66：I_O and Packaging (39分15秒)
- 课时67：11a_ Sign-off Timing (13分3秒)
- 课时68：11b- Additional issues in Sign-off Timing (11分25秒)
- 课时69：11c_ Chip Finishing, including Density Fill and Antenna Fixes (11分21秒)
- 课时70： 11d- Sign-off Validation, including IR Drop and EM Analysis, LEC, and DRC_LVS_ERC (18分53秒)
- 课时71：Chip Finishing and Signoff (32分33秒)
- 课时72：Introduction to Tcl-The tool command language-Part1 (18分5秒)
- 课时73：Introduction to Tcl-The tool command language-Part2 (15分3秒)
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