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- Verilog HDL
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课时1:1a Introduction
课时2:1b Building a Chip
课时3:1c Design Automation
课时4:1d The Chip Design Flow
课时5:Introduction
课时6:2a_ Verilog
课时7:2b_ Verilog Syntax
课时8:2c_ Simple Verilog Examples
课时9:2d_ Verilog FSM Implementation
课时10:2e- Coding Style for RTL - part 1
课时11:How to write Synthesizeable RTL
课时12:Verilog HDL
课时13:3a_ Logic Synthesis - Part 1
课时14:3b_ HDL Compilation
课时15:3c- Library Definition
课时16:3d- LEF
课时17:3e_ Liberty (.lib)
课时18:3f- Contents of Standard Cell Libraries
课时19:Logic Synthesis Part 1
课时20:4a_ Logic Synthesis - Part 2
课时21:4b_ BDDs and Boolean Minimization
课时22:4c_ Constraint Definition
课时23:4d_ Technology Mapping
课时24:4e_ Verilog for Synthesis - revisited
课时25:4f- Timing Optimization
课时26:Logic Synthesis Part 2
课时27:5a_ Timing Analysis
课时28:5b_ Timing Constraints
课时29:5c_ Static Timing Analysis (STA)
课时30:5d_ STA Example
课时31:5e_ Design Constraints (SDC)
课时32:5f_ SDC Continued.
课时33:5g_ Timing Reports
课时34:5h_ Multi-Mode Multi-Corner (MMMC)
课时35:Timing Analysis
课时36:6a_ Moving to the Physical Domain
课时37:6b- Multiple Voltage Domains
课时38:6c_ Floorplanning
课时39:6d_ Hierarchical Design
课时40:6e- Power Planning
课时41:Moving to the Physical Domain
课时42:7a_ Standard Cell Placement
课时43:7b_ Random Placement
课时44:7c_ Analytic Placement
课时45:7d- Analytic Placement Example
课时46:7e_ Placement in Practice
课时47:Placement
课时48:8a_ Clock Tree Synthesis (CTS)
课时49:8b_ Clock Distribution
课时50:8c_ Clock Concurrent Optimization (CCOpt)
课时51:8d- Clock Tree Synthesis in EDA Tools
课时52:8e_ Clock Routing and Clock Tree Analysis
课时53:8f_ Clock Generation
课时54:8g_ Clock Domain Crossing (CDC)
课时55:CTS
课时56:9a- Routing
课时57:9b_ Maze Routing
课时58:9c_ Maze Routing (continued)
课时59:9d- Routing in Practice
课时60:9e- Signal Integrity (SI) and Design for Manufacturing (DFM)
课时61:Routing
课时62:10a- Packaging
课时63:10b- I_O Circuits - Digital IOs
课时64:10c- I_O Circuits - Analog IOs, ESD Protection, Pad Configurations
课时65:10d- System-in-Package (SiP)
课时66:I_O and Packaging
课时67:11a_ Sign-off Timing
课时68:11b- Additional issues in Sign-off Timing
课时69:11c_ Chip Finishing, including Density Fill and Antenna Fixes
课时70: 11d- Sign-off Validation, including IR Drop and EM Analysis, LEC, and DRC_LVS_ERC
课时71:Chip Finishing and Signoff
课时72:Introduction to Tcl-The tool command language-Part1
课时73:Introduction to Tcl-The tool command language-Part2
课程介绍共计73课时,19小时57分0秒
In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture slides can be found on the EnICS Labs web site at:
https://enicslabs.com/academic-courses/dvd-english/